Timothy Pearson
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eb6afe10e6
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Add a several cycle "dead zone" to 7-segment decoder segment select lines to more accurately emulate real hardware
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5 years ago |
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Timothy Pearson
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9db454faca
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Slow demo file 7-segment clock to a more reasonable KHz value
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5 years ago |
|
Timothy Pearson
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d64d218d18
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Fix incorrect pin assignment for 7-segment LED display
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5 years ago |
|
Timothy Pearson
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894b7938b3
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Correctly implement 7-segment display LED persistence
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5 years ago |
|
Timothy Pearson
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1733ea93c9
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Enable remaining I/O busses on Lattice control FPGA
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5 years ago |
|
Timothy Pearson
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f8f6ee88d8
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Add test program for Lattice guest FPGAs
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5 years ago |
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Timothy Pearson
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cd7e1ea3b8
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Add user logic reset support to serial version of FPGA control interface
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5 years ago |
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Timothy Pearson
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e1a4f6f17e
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Add intial version of Lattice remote FPGA interface
Minor tweaks to core remote FPGA file to eliminate Yosys warnings and reduce design size
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5 years ago |
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Timothy Pearson
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e1e7c9e49d
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Modify FPGA interface license to AGPL v3
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5 years ago |
Timothy Pearson
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46155f46b1
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Update copyright dates
|
5 years ago |
|
Timothy Pearson
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6ed57d34ca
|
First pass of logic analyzer functionality (GPMC interface and server)
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10 years ago |
|
Timothy Pearson
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1fbfe13066
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First pass of logic analyzer functionality (client and FPGA core)
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10 years ago |
|
Timothy Pearson
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72e80dda8e
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Add ability to hard reset user device
Fix initial size of serial and terminal windows
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10 years ago |
|
Timothy Pearson
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2dc576d25f
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Hard reset user device on connection and disconnection of FPGA viewer
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10 years ago |
|
Timothy Pearson
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038275fcc0
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Add serial I/O to host FPGA
|
10 years ago |
|
Timothy Pearson
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dc91899c25
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Add initial version of a logic analyzer server
|
10 years ago |
|
Timothy Pearson
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061289c613
|
Max out logic analyzer memory
|
10 years ago |
|
Timothy Pearson
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13aee3afa9
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Merge branch 'master' of http://scm.trinitydesktop.org/scm/git/remotelaboratory
|
10 years ago |
|
Timothy Pearson
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1eb48edeba
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Add logic analyzer block to control FPGA
|
10 years ago |
|
Timothy Pearson
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32b7b87d3d
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Lower the uLab FPGA viewer GPMC clock to reduce errors on prototype lashup
Add memory stress tests to GPMC test program
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10 years ago |
|
Timothy Pearson
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0ffb793cb5
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Relayout the GUI to be more in line with expected norms
Add user logic reset signal
Stabilize data transfer
|
10 years ago |
|
Timothy Pearson
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37420cfb78
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Increase DSP memory size
Fix potential crash in FPGA viewer if hardware debug interface is malfunctioning or offline
|
10 years ago |
|
Timothy Pearson
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a4eb2fb6bf
|
Move hardware design files to their correct locations
|
10 years ago |
|
Timothy Pearson
|
04ab7c6632
|
Add initial GOMC compatible uLab debug system hardware design files
|
10 years ago |
|
Timothy Pearson
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963b88fb0b
|
Add initial GPMC test program and associated files for BeagleBone Black
|
10 years ago |
|
Timothy Pearson
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38c56c7c1f
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Add initial version of SVF player for Beaglebone Black
|
10 years ago |
|
Timothy Pearson
|
26c1236cdc
|
Fix prior commit
|
11 years ago |
|
Timothy Pearson
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5c2d024b38
|
Fix progress bar not moving during DSP data reception
Fix syntax error in demo main.v file
|
11 years ago |
|
Timothy Pearson
|
8ce60c7f52
|
Fix prior commit
|
11 years ago |
|
Timothy Pearson
|
f27e0f0184
|
Allow data processing RAM size to be configured by changing a Verilog parameter on the FPGA side
|
11 years ago |
|
Timothy Pearson
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8faa3da109
|
Fix image distortion when certain greyscale values are utilized
Store last used values in FPGA viewer and programmer GUI for convenience on GUI restart
|
11 years ago |
|
Timothy Pearson
|
ff484b9d9c
|
Fix 7 segment display malfunction at low multiplexing rates
|
11 years ago |
|
Timothy Pearson
|
7997af3f4f
|
Fix 7-segment LED display and add sample driver for the same
|
11 years ago |
|
Timothy Pearson
|
976f4c5dfe
|
Use 10-pin headers for ulab debug interface serial port on Spartan 6
|
11 years ago |
|
Timothy Pearson
|
3f00d517b8
|
Add sample image processing module to Spartan 6 demo project
|
11 years ago |
|
Timothy Pearson
|
401379667e
|
Properly report device programming errors
|
11 years ago |
|
Timothy Pearson
|
400d0abcff
|
Avoid usage of TQTimer::singleShot in the FPGA viewer part
Repair "think-o" in the Spartan 6 block RAM HDL
|
11 years ago |
|
Timothy Pearson
|
9d5b0368df
|
Add sample design for Spartan 6 and ISE 14.4
|
11 years ago |
|
Timothy Pearson
|
40acabc2bf
|
Update remote debug module and clean up FPGA section of the source tree
|
11 years ago |
|
Timothy Pearson
|
1e0e205356
|
Add verified Xilinx programming script and device type extractor
|
12 years ago |
|
Timothy Pearson
|
f1ead12600
|
Minor cleanup
|
12 years ago |
|
Timothy Pearson
|
f0c477eef4
|
Add magic 64 bytes to S6 svf file
|
12 years ago |
|
Timothy Pearson
|
d94bf35fe7
|
Add initial untested support for Spartan 6 devices
|
12 years ago |
|
Timothy Pearson
|
9c6d284d49
|
Initial rpi jtag support
|
12 years ago |
|
Timothy Pearson
|
7643298424
|
Update makefiles
|
12 years ago |
|
Timothy Pearson
|
d1b70f8018
|
Add initial files for direct FPGA programming
|
12 years ago |
|
Timothy Pearson
|
db7e77be8f
|
Add public domain FPGA files for Xilinx s3/s3e
|
12 years ago |
