First pass of logic analyzer functionality (client and FPGA core)

master
Timothy Pearson 10 years ago
parent 6ae28a47f7
commit 1fbfe13066

@ -1 +1 @@
SUBDIRS = scope commanalyzer fpgaview fpgaprogram sensormonitor adminconsole adminusermgmt serialconsole prototerminal
SUBDIRS = scope logicanalyzer commanalyzer fpgaview fpgaprogram sensormonitor adminconsole adminusermgmt serialconsole prototerminal

@ -89,7 +89,7 @@ CommAnalyzerPart::CommAnalyzerPart( TQWidget *parentWidget, const char *widgetNa
m_traceWidget->setZoomBoxEnabled(true);
m_base->traceZoomWidget->setSizePolicy(TQSizePolicy(TQSizePolicy::MinimumExpanding, TQSizePolicy::MinimumExpanding));
m_base->traceZoomWidget->setTraceEnabled(0, true, false);
m_base->traceZoomWidget->setTraceEnabled(0, true, TraceWidget::SummaryText);
m_base->traceZoomWidget->setTraceName(0, "Trace 1");
m_base->traceZoomWidget->setTraceHorizontalUnits(0, "Hz");
m_base->traceZoomWidget->setTraceVerticalUnits(0, "dBm");

@ -0,0 +1,12 @@
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<!DOCTYPE UI><UI version="3.0" stdsetdef="1">
<class>LogicAnalyzerBase</class>
<widget class="TQWidget">
<property name="name">
<cstring>LogicAnalyzerBase</cstring>
</property>
<property name="geometry">
<rect>
<x>0</x>
<y>0</y>
<width>519</width>
<height>356</height>
</rect>
</property>
<grid>
<property name="name">
<cstring>unnamed</cstring>
</property>
<widget class="TQGroupBox" row="0" column="0">
<property name="name">
<cstring>groupLogicAnalyzer</cstring>
</property>
<property name="title">
<string>Logic Analyzer</string>
</property>
<grid>
<property name="name">
<cstring>unnamed</cstring>
</property>
<widget class="TQGroupBox" row="0" column="0" rowspan="10">
<property name="name">
<cstring>groupLogicAnalyzerView</cstring>
</property>
<property name="title">
<string>Trace Viewer</string>
</property>
<property name="sizePolicy">
<sizepolicy>
<hsizetype>7</hsizetype>
<vsizetype>7</vsizetype>
<horstretch>1</horstretch>
<verstretch>1</verstretch>
</sizepolicy>
</property>
<grid>
<property name="name">
<cstring>unnamed</cstring>
</property>
<widget class="TQSplitter" row="0" column="0" colspan="1">
<property name="name">
<cstring>splitter1</cstring>
</property>
<property name="orientation">
<enum>Vertical</enum>
</property>
<widget class="TraceScrollWidget" row="0" column="0" colspan="1">
<property name="name">
<cstring>traceScrollWidget</cstring>
</property>
<property name="minimumSize">
<size>
<width>0</width>
<height>0</height>
</size>
</property>
<property name="resizePolicy">
<enum>AutoOneFit</enum>
</property>
</widget>
</widget>
</grid>
</widget>
<widget class="TQGroupBox" row="0" column="1">
<property name="name">
<cstring>groupLogicAnalyzerCaptureControls</cstring>
</property>
<property name="title">
<string>Capture Controls</string>
</property>
<grid>
<widget class="TQPushButton" row="0" column="0" colspan="1">
<property name="name">
<cstring>runControlStartButton</cstring>
</property>
<property name="text">
<string>Run</string>
</property>
</widget>
<widget class="TQPushButton" row="0" column="1" colspan="1">
<property name="name">
<cstring>runControlStopButton</cstring>
</property>
<property name="text">
<string>Stop</string>
</property>
</widget>
<widget class="TQWidget" row="1" column="0" colspan="2">
<property name="name">
<cstring>traceControlLayoutWidget</cstring>
</property>
</widget>
</grid>
</widget>
<widget class="TQGroupBox" row="1" column="1">
<property name="name">
<cstring>groupLogicAnalyzerAcquisitionControls</cstring>
</property>
<property name="title">
<string>Acquisition Controls</string>
</property>
<grid>
<widget class="TQPushButton" row="0" column="0" colspan="1">
<property name="name">
<cstring>acqStart</cstring>
</property>
<property name="text">
<string>Start Acquisition</string>
</property>
</widget>
<widget class="TQPushButton" row="0" column="1" colspan="1">
<property name="name">
<cstring>acqStop</cstring>
</property>
<property name="text">
<string>Stop Acquisition</string>
</property>
</widget>
<widget class="TQPushButton" row="1" column="0" colspan="1">
<property name="name">
<cstring>waveformSave</cstring>
</property>
<property name="text">
<string>Save Waveforms</string>
</property>
</widget>
<widget class="TQPushButton" row="1" column="1" colspan="1">
<property name="name">
<cstring>waveformRecall</cstring>
</property>
<property name="text">
<string>Recall Waveforms</string>
</property>
</widget>
</grid>
</widget>
</grid>
</widget>
</grid>
</widget>
<includes>
<include location="local" impldecl="in implementation">LogicAnalyzerBase.ui.h</include>
</includes>
<includes>
<include location="local" impldecl="in implementation">tracewidget.h</include>
<include location="local" impldecl="in implementation">floatspinbox.h</include>
</includes>
<layoutdefaults spacing="3" margin="6"/>
<layoutfunctions spacing="KDialog::spacingHint" margin="KDialog::marginHint"/>
</UI>

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//Author: Timothy Pearson <kb9vqf@pearsoncomputing.net>, (C) 2014
//Copyright: See COPYING file that comes with this distribution
#ifndef REMOTELAB_LOGICANALYZERPART_H
#define REMOTELAB_LOGICANALYZERPART_H
#include <tdeparts/browserextension.h>
#include <tdeparts/statusbarextension.h>
#include <tdeparts/part.h>
#include <kurl.h>
#include <tqtrla.h>
#define MAXTRACES 255
class TDEAboutData;
using KParts::StatusBarExtension;
class TraceWidget;
class TQSocket;
class TQTimer;
class TQMutex;
class TQRectF;
class TQGridLayout;
class TQCheckBox;
class TQGroupBox;
class LogicAnalyzerBase;
namespace RemoteLab
{
class LogicAnalyzerPart : public KParts::RemoteInstrumentPart
{
Q_OBJECT
public:
LogicAnalyzerPart( QWidget *, const char *, TQObject *, const char *, const TQStringList&);
~LogicAnalyzerPart();
virtual bool openFile() { return false; } // pure virtual in the base class
virtual bool closeURL();
static TDEAboutData *createAboutData();
public slots:
virtual bool openURL(const KURL &url);
private slots:
void postInit();
void processLockouts();
void updateGraticule();
void connectionFinishedCallback();
void disconnectFromServerCallback();
void connectionStatusChangedCallback();
void setTickerMessage(TQString message);
void mainEventLoop();
void startDAQ();
void stopDAQ();
void startLogicAnalyzer();
void stopLogicAnalyzer();
void saveWaveforms();
void recallWaveforms();
virtual void postProcessTrace();
private:
TraceWidget* m_traceWidget;
TQGridLayout* m_traceControlWidgetGrid;
int m_commHandlerState;
int m_commHandlerMode;
int m_commHandlerCommandState;
TQTimer* m_forcedUpdateTimer;
TQTimer* m_updateTimeoutTimer;
bool m_connectionActiveAndValid;
unsigned char m_tickerState;
TQ_INT16 m_maxNumberOfTraces;
TQ_INT32 m_currentOpChannel;
TQ_INT32 m_nextOpChannel;
TQ_INT16 m_nextOpParameter16;
TQ_INT16 m_hdivs;
TQ_INT16 m_vdivs;
bool m_running;
TQ_INT32 m_samplesInTrace[MAXTRACES+1];
bool m_channelActive[MAXTRACES+1];
TQString m_channelName[MAXTRACES+1];
double m_voltsDiv[MAXTRACES+1];
double m_secsDiv[MAXTRACES+1];
bool m_runningSet;
bool m_voltsDivSet[MAXTRACES+1];
bool m_channelActiveSet[MAXTRACES+1];
bool m_lastChangesRequireFullUpdate;
LogicAnalyzerBase* m_base;
TQMutex* m_instrumentMutex;
bool stopTraceUpdate;
};
}
#endif

@ -681,7 +681,7 @@ void ScopePart::mainEventLoop() {
m_socket->clearFrameTail();
if (result == "ACK") {
if (m_currentOpChannel < m_maxNumberOfTraces) {
if (m_currentOpChannel < (m_maxNumberOfTraces-1)) {
m_currentOpChannel++;
SET_NEXT_STATE(ScopeState_ChannelActiveStateRequest)
}
@ -799,7 +799,7 @@ void ScopePart::mainEventLoop() {
m_socket->clearFrameTail();
if (result == "ACK") {
if (m_currentOpChannel < m_maxNumberOfTraces) {
if (m_currentOpChannel < (m_maxNumberOfTraces-1)) {
m_currentOpChannel++;
SET_NEXT_STATE(ScopeState_TracePermittedVoltsDivRequest)
}
@ -1178,7 +1178,7 @@ void ScopePart::mainEventLoop() {
SET_NEXT_STATE_DATA_WAITING(ScopeState_ChannelActiveStateUpdate+1)
}
else {
if (m_currentOpChannel < m_maxNumberOfTraces) {
if (m_currentOpChannel < (m_maxNumberOfTraces-1)) {
m_currentOpChannel++;
SET_NEXT_STATE(ScopeState_ChannelActiveStateUpdate)
}
@ -1646,20 +1646,20 @@ void ScopePart::updateGraticule() {
if (m_maxNumberOfTraces > 3) m_base->traceZoomWidget->setTraceColor(3, TQColor(128, 128, 255));
for (int traceno=1; traceno<=m_maxNumberOfTraces; traceno++) {
m_traceWidget->setTraceEnabled(traceno-1, m_channelActive[traceno]);
m_traceWidget->setTraceName(traceno-1, TQString("Channel %1").arg(traceno));
m_traceWidget->setTraceHorizontalUnits(traceno-1, "s");
m_traceWidget->setTraceVerticalUnits(traceno-1, "V");
m_traceWidget->setTraceEnabled(traceno-1, m_channelActive[traceno], TraceWidget::FullText, true);
m_traceWidget->setTraceName(traceno-1, TQString("Channel %1").arg(traceno), true);
m_traceWidget->setTraceHorizontalUnits(traceno-1, "s", true);
m_traceWidget->setTraceVerticalUnits(traceno-1, "V", true);
m_base->traceZoomWidget->setTraceEnabled(traceno-1, m_channelActive[traceno], false);
m_base->traceZoomWidget->setTraceName(traceno-1, TQString("Channel %1").arg(traceno));
m_base->traceZoomWidget->setTraceHorizontalUnits(traceno-1, "s");
m_base->traceZoomWidget->setTraceVerticalUnits(traceno-1, "V");
m_base->traceZoomWidget->setTraceEnabled(traceno-1, m_channelActive[traceno], TraceWidget::SummaryText, true);
m_base->traceZoomWidget->setTraceName(traceno-1, TQString("Channel %1").arg(traceno), true);
m_base->traceZoomWidget->setTraceHorizontalUnits(traceno-1, "s", true);
m_base->traceZoomWidget->setTraceVerticalUnits(traceno-1, "V", true);
m_traceWidget->setNumberOfSamples(traceno-1, m_samplesInTrace[traceno]);
m_base->traceZoomWidget->setNumberOfSamples(traceno-1, m_samplesInTrace[traceno]);
m_traceWidget->setNumberOfSamples(traceno-1, m_samplesInTrace[traceno], true);
m_base->traceZoomWidget->setNumberOfSamples(traceno-1, m_samplesInTrace[traceno], (traceno<m_maxNumberOfTraces)?true:false);
m_traceWidget->setDisplayLimits(traceno-1, TQRectF(0.0, (m_voltsDiv[traceno]*m_vdivs)/2.0, (m_secsDiv[traceno]*m_hdivs), (m_voltsDiv[traceno]*m_vdivs)/-2.0));
m_traceWidget->setDisplayLimits(traceno-1, TQRectF(0.0, (m_voltsDiv[traceno]*m_vdivs)/2.0, (m_secsDiv[traceno]*m_hdivs), (m_voltsDiv[traceno]*m_vdivs)/-2.0), (traceno<m_maxNumberOfTraces)?true:false);
if (m_traceControlWidgetList[traceno-1]) {
m_traceControlWidgetList[traceno-1]->setSelectedVoltsPerDiv(m_voltsDiv[traceno]);
m_traceControlWidgetList[traceno-1]->setTraceEnabled(m_channelActive[traceno]);

@ -696,7 +696,7 @@ void SensorMonitorPart::updateGraticule() {
m_traceWidget->setTraceHorizontalUnits(traceno, "s");
m_traceWidget->setTraceVerticalUnits(traceno, m_sensorList[traceno].units);
m_base->traceZoomWidget->setTraceEnabled(traceno, m_channelActive[traceno], false);
m_base->traceZoomWidget->setTraceEnabled(traceno, m_channelActive[traceno], TraceWidget::SummaryText);
m_base->traceZoomWidget->setTraceName(traceno, i18n("Sensor %1").arg(m_sensorList[traceno].name));
m_base->traceZoomWidget->setTraceHorizontalUnits(traceno, "s");
m_base->traceZoomWidget->setTraceVerticalUnits(traceno, m_sensorList[traceno].units);

@ -205,7 +205,7 @@ void TraceLabelLayout::setGeometry(const TQRect &rect) {
int font_vertical_offset = font_height/2;
int graticule_height = m_traceWidget->m_graticuleWidget->height();
int y = (((currentTrace->offset-currentTrace->topEdge)/(currentTrace->bottomEdge-currentTrace->topEdge))*(graticule_height))-font_vertical_offset;
int y = ((((currentTrace->offset+currentTrace->textOffset)-currentTrace->topEdge)/(currentTrace->bottomEdge-currentTrace->topEdge))*(graticule_height))-font_vertical_offset;
if (m_traceWidget->m_showLeftTraceInfoArea) {
if ((y < 0) || ((y+font_height) > graticule_height)) {
currentTrace->leftLabel->hide();
@ -228,6 +228,7 @@ void TraceLabelLayout::invalidate() {
TQSize TraceLabelLayout::sizeHint() const
{
TQSize size;
if (!m_traceWidget->m_showLeftTraceInfoArea) {
return TQSize(0, 0);
}
@ -239,11 +240,19 @@ TQSize TraceLabelLayout::sizeHint() const
++it;
s = s.expandedTo(item->sizeHint());
}
return s + TQSize(spacing(), spacing());
size = s + TQSize(spacing(), spacing());
if (m_traceWidget->m_leftTraceInfoLabelsFit && list.getFirst()) {
return TQSize(size.width(), ((list.getFirst()->sizeHint().height() + m_traceWidget->m_leftTraceInfoAreaFitSpacing) * list.count()));
}
else {
return size;
}
}
TQSize TraceLabelLayout::minimumSize() const
{
TQSize minSize;
if (!m_traceWidget->m_showLeftTraceInfoArea) {
return TQSize(0, 0);
}
@ -255,7 +264,14 @@ TQSize TraceLabelLayout::minimumSize() const
++it;
s = s.expandedTo(item->minimumSize());
}
return s + TQSize(spacing(), spacing());
minSize = s + TQSize(spacing(), spacing());
if (m_traceWidget->m_leftTraceInfoLabelsFit && list.getFirst()) {
return TQSize(minSize.width(), ((list.getFirst()->minimumSize().height()+ m_traceWidget->m_leftTraceInfoAreaFitSpacing) * list.count()));
}
else {
return minSize;
}
}
TraceData::TraceData(TraceWidget* parent, TQWidget* labelParent) : TQObject(), parentWidget(parent) {
@ -264,6 +280,7 @@ TraceData::TraceData(TraceWidget* parent, TQWidget* labelParent) : TQObject(), p
leftEdgeIndex = -1;
rightEdgeIndex = -1;
offset = 0.0;
textOffset = 0.0;
leftEdge = 0;
rightEdge = 0;
topEdge = 0;
@ -286,7 +303,7 @@ TraceData::TraceData(TraceWidget* parent, TQWidget* labelParent) : TQObject(), p
leftLabel = new TQLabel(labelParent);
leftLabel->setPaletteBackgroundColor(labelParent->paletteBackgroundColor());
leftLabel->setPaletteForegroundColor(color);
leftLabel->setAlignment(TQt::AlignHCenter|TQt::AlignVCenter|TQt::SingleLine);
leftLabel->setAlignment(TQt::AlignLeft|TQt::AlignVCenter|TQt::SingleLine);
font = leftLabel->font();
font.setPointSize(font.pointSize()-1);
leftLabel->setFont(font);
@ -421,7 +438,7 @@ void TraceData::drawTrace(TQPainter* p, int graticule_width, int graticule_heigh
int font_height = p->fontMetrics().boundingRect("").height();
x = 0;
y = (((offset-topEdge)/(bottomEdge-topEdge))*(graticule_height))+(font_height/2)-(font_vertical_offset/2);
y = ((((offset+textOffset)-topEdge)/(bottomEdge-topEdge))*(graticule_height))+(font_height/2)-(font_vertical_offset/2);
if (y > graticule_height) {
font_height = p->fontMetrics().boundingRect("").height();
y = graticule_height-font_vertical_offset;
@ -1047,7 +1064,10 @@ TraceWidget::TraceWidget(TQWidget* parent, const char* name) : TQWidget(parent,
m_zoomCursorStartIndex(0),
m_zoomBoxEnabled(false),
m_useAbsoluteHorizontalRange(true),
m_showLeftTraceInfoArea(false) {
m_showLeftTraceInfoArea(false),
m_leftTraceInfoLabelsFit(false),
m_leftTraceInfoAreaFitSpacing(0),
m_minimumPixelsPerHorizDiv(0) {
setBackgroundMode(NoBackground);
setSizePolicy(TQSizePolicy(TQSizePolicy::MinimumExpanding, TQSizePolicy::MinimumExpanding));
@ -1115,17 +1135,28 @@ void TraceWidget::setBackgroundColor(const TQColor color) {
}
}
void TraceWidget::setNumberOfSamples(uint traceNumber, unsigned int samples) {
void TraceWidget::setNumberOfSamples(uint traceNumber, unsigned int samples, bool deferUpdate) {
VERIFY_TRACE_ARRAY_SIZE
int i;
int prev_samples = m_traceArray[traceNumber]->sampleArray.count();
m_traceArray[traceNumber]->numberOfSamples = samples;
m_traceArray[traceNumber]->sampleArray.resize(samples);
m_traceArray[traceNumber]->positionArray.resize(samples);
m_traceArray[traceNumber]->leftEdgeIndex = -1;
m_traceArray[traceNumber]->rightEdgeIndex = -1;
m_graticuleWidget->updateGraticule();
updateTraceText();
// Zero the uninitialized portion of the data arrays to avoid ugly drawing artifacts on resize
for (i=prev_samples; i<samples; i++) {
m_traceArray[traceNumber]->sampleArray[i] = 0;
m_traceArray[traceNumber]->positionArray[i] = 0;
}
if (!deferUpdate) {
m_graticuleWidget->updateGraticule();
updateTraceText();
}
}
void TraceWidget::setNumberOfHorizontalDivisions(unsigned int divisions) {
@ -1142,7 +1173,7 @@ void TraceWidget::setNumberOfVerticalDivisions(unsigned int divisions) {
updateCursorText();
}
void TraceWidget::setDisplayLimits(uint traceNumber, TQRectF limits) {
void TraceWidget::setDisplayLimits(uint traceNumber, TQRectF limits, bool deferUpdate) {
VERIFY_TRACE_ARRAY_SIZE
m_traceArray[traceNumber]->leftEdge = limits.x();
@ -1152,10 +1183,12 @@ void TraceWidget::setDisplayLimits(uint traceNumber, TQRectF limits) {
m_traceArray[traceNumber]->leftEdgeIndex = -1;
m_traceArray[traceNumber]->rightEdgeIndex = -1;
m_graticuleWidget->updateGraticule();
m_graticuleWidget->repaint(false);
updateTraceText();
updateCursorText();
if (!deferUpdate) {
m_graticuleWidget->updateGraticule();
m_graticuleWidget->repaint(false);
updateTraceText();
updateCursorText();
}
}
TQRectF TraceWidget::displayLimits(uint traceNumber) {
@ -1266,13 +1299,15 @@ TQDoubleArray& TraceWidget::samples(uint traceNumber) {
return m_traceArray[traceNumber]->sampleArray;
}
void TraceWidget::setSamples(uint traceNumber, TQDoubleArray& tqda) {
void TraceWidget::setSamples(uint traceNumber, TQDoubleArray& tqda, bool deferUpdate) {
VERIFY_TRACE_ARRAY_SIZE
m_traceArray[traceNumber]->sampleArray = tqda;
m_traceArray[traceNumber]->numberOfSamples = tqda.size();
m_graticuleWidget->repaint(false);
if (!deferUpdate) {
m_graticuleWidget->repaint(false);
}
}
TQDoubleArray& TraceWidget::positions(uint traceNumber) {
@ -1281,7 +1316,7 @@ TQDoubleArray& TraceWidget::positions(uint traceNumber) {
return m_traceArray[traceNumber]->positionArray;
}
void TraceWidget::setPositions(uint traceNumber, TQDoubleArray& tqda) {
void TraceWidget::setPositions(uint traceNumber, TQDoubleArray& tqda, bool deferUpdate) {
VERIFY_TRACE_ARRAY_SIZE
m_traceArray[traceNumber]->positionArray = tqda;
@ -1289,7 +1324,9 @@ void TraceWidget::setPositions(uint traceNumber, TQDoubleArray& tqda) {
m_traceArray[traceNumber]->leftEdgeIndex = -1;
m_traceArray[traceNumber]->rightEdgeIndex = -1;
m_graticuleWidget->repaint(false);
if (!deferUpdate) {
m_graticuleWidget->repaint(false);
}
}
TQColor TraceWidget::traceColor(uint traceNumber) {
@ -1314,12 +1351,12 @@ bool TraceWidget::traceEnabled(uint traceNumber) {
return m_traceArray[traceNumber]->enabled;
}
void TraceWidget::setTraceEnabled(uint traceNumber, bool enabled, bool showText) {
void TraceWidget::setTraceEnabled(uint traceNumber, bool enabled, TextDisplayType showText, bool deferUpdate) {
VERIFY_TRACE_ARRAY_SIZE
m_traceArray[traceNumber]->enabled = enabled;
if (enabled) {
if (showText) {
if (showText == FullText) {
m_traceArray[traceNumber]->paramLabel->show();
m_traceArray[traceNumber]->leftLabel->show();
m_traceArray[traceNumber]->graphStatusLabel->show();
@ -1333,7 +1370,12 @@ void TraceWidget::setTraceEnabled(uint traceNumber, bool enabled, bool showText)
m_traceArray[traceNumber]->paramLabel->hide();
m_traceArray[traceNumber]->leftLabel->hide();
m_traceArray[traceNumber]->graphStatusLabel->hide();
m_traceArray[traceNumber]->graphStatusLabelInner->show();
if (showText == SummaryText) {
m_traceArray[traceNumber]->graphStatusLabelInner->show();
}
else {
m_traceArray[traceNumber]->graphStatusLabelInner->hide();
}
m_traceArray[traceNumber]->singleIncrBtn->hide();
m_traceArray[traceNumber]->singleDecrBtn->hide();
m_traceArray[traceNumber]->posResetBtn->hide();
@ -1351,9 +1393,11 @@ void TraceWidget::setTraceEnabled(uint traceNumber, bool enabled, bool showText)
m_traceArray[traceNumber]->posSetBtn->hide();
}
m_graticuleWidget->updateGraticule();
m_graticuleWidget->repaint(false);
updateTraceText();
if (!deferUpdate) {
m_graticuleWidget->updateGraticule();
m_graticuleWidget->repaint(false);
updateTraceText();
}
}
TQString TraceWidget::traceName(uint traceNumber) {
@ -1362,11 +1406,13 @@ TQString TraceWidget::traceName(uint traceNumber) {
return m_traceArray[traceNumber]->traceName;
}
void TraceWidget::setTraceName(uint traceNumber, TQString name) {
void TraceWidget::setTraceName(uint traceNumber, TQString name, bool deferUpdate) {
VERIFY_TRACE_ARRAY_SIZE
m_traceArray[traceNumber]->traceName = name;
updateTraceText();
if (!deferUpdate) {
updateTraceText();
}
}
TQString TraceWidget::traceHorizontalUnits(uint traceNumber) {
@ -1375,11 +1421,13 @@ TQString TraceWidget::traceHorizontalUnits(uint traceNumber) {
return m_traceArray[traceNumber]->horizontalUnits;
}
void TraceWidget::setTraceHorizontalUnits(uint traceNumber, TQString units) {
void TraceWidget::setTraceHorizontalUnits(uint traceNumber, TQString units, bool deferUpdate) {
VERIFY_TRACE_ARRAY_SIZE
m_traceArray[traceNumber]->horizontalUnits = units;
updateTraceText();
if (!deferUpdate) {
updateTraceText();
}
}
TQString TraceWidget::traceVerticalUnits(uint traceNumber) {
@ -1388,11 +1436,13 @@ TQString TraceWidget::traceVerticalUnits(uint traceNumber) {
return m_traceArray[traceNumber]->verticalUnits;
}
void TraceWidget::setTraceVerticalUnits(uint traceNumber, TQString units) {
void TraceWidget::setTraceVerticalUnits(uint traceNumber, TQString units, bool deferUpdate) {
VERIFY_TRACE_ARRAY_SIZE
m_traceArray[traceNumber]->verticalUnits = units;
updateTraceText();
if (!deferUpdate) {
updateTraceText();
}
}
double TraceWidget::cursorPosition(uint cursorNumber) {
@ -1714,6 +1764,20 @@ void TraceWidget::showLeftTraceInfoArea(bool show) {
}
}
void TraceWidget::fitLeftTraceInfoArea(bool fit) {
m_leftTraceInfoLabelsFit = fit;
m_traceLeftLabelLayout->invalidate();
}
void TraceWidget::setLeftTraceInfoAreaFitSpacing(int spacing) {
m_leftTraceInfoAreaFitSpacing = spacing;
m_traceLeftLabelLayout->invalidate();
}
void TraceWidget::setMinimumPixelsPerHorizDiv(unsigned int pixels) {
m_minimumPixelsPerHorizDiv = pixels;
}
TQString TraceWidget::prettyFormat(double value, double rangeDetectValue, TQString baseUnits, unsigned int precision) {
TQString result;
TQString unitMultiplier;
@ -1789,12 +1853,39 @@ double TraceWidget::traceOffset(uint traceNumber) {
}
void TraceWidget::setTraceOffset(uint traceNumber, double offset) {
setTraceOffset(traceNumber, offset, false);
}
void TraceWidget::setTraceOffset(uint traceNumber, double offset, bool deferUpdate) {
VERIFY_TRACE_ARRAY_SIZE
m_traceArray[traceNumber]->offset = offset;
m_graticuleWidget->repaint(false);
updateTraceText();
if (!deferUpdate) {
m_graticuleWidget->repaint(false);
updateTraceText();
}
}
double TraceWidget::traceTextOffset(uint traceNumber) {
VERIFY_TRACE_ARRAY_SIZE
return m_traceArray[traceNumber]->textOffset;
}
void TraceWidget::setTraceTextOffset(uint traceNumber, double offset) {
setTraceOffset(traceNumber, offset, false);
}
void TraceWidget::setTraceTextOffset(uint traceNumber, double offset, bool deferUpdate) {
VERIFY_TRACE_ARRAY_SIZE
m_traceArray[traceNumber]->textOffset = offset;
if (!deferUpdate) {
m_graticuleWidget->repaint(false);
updateTraceText();
}
}
void TraceWidget::processChangedOffset(double offset) {
@ -1904,6 +1995,16 @@ void TraceWidget::resizeCursorArray(uint newsize) {
}
}
TQSize TraceWidget::sizeHint() const {
TQSize widgetSizeHint = TQWidget::sizeHint();
unsigned int minimumHorizWidth = m_horizDivs * m_minimumPixelsPerHorizDiv;
return TQSize(TQMAX(minimumHorizWidth, widgetSizeHint.height()), widgetSizeHint.height());
}
TQSize TraceWidget::minimumSizeHint() const {
return TQWidget::minimumSizeHint();
}
TraceScrollWidget::TraceScrollWidget(TQWidget* parent, const char* name) : TQScrollView(parent, name) {
m_traceWidget = new TraceWidget(viewport());
addChild(m_traceWidget);
@ -1915,7 +2016,7 @@ TraceScrollWidget::~TraceScrollWidget() {
}
TQSize TraceScrollWidget::sizeHint() const {
return m_traceWidget->sizeHint();
return TQScrollView::sizeHint();
}
TQSize TraceScrollWidget::minimumSizeHint() const {

@ -71,6 +71,7 @@ class TraceData : public TQObject
long leftEdgeIndex;
long rightEdgeIndex;
double offset;
double textOffset;
TQColor color;
bool enabled;
double leftEdge;
@ -187,33 +188,40 @@ class GraticuleWidget : public TQWidget
class TraceWidget : public TQWidget
{
Q_OBJECT
public:
enum TextDisplayType {
FullText,
SummaryText,
NoText
};
public:
TraceWidget(TQWidget* = 0, const char* = 0);
~TraceWidget();
void setNumberOfSamples(uint traceNumber, unsigned int samples);
void setNumberOfSamples(uint traceNumber, unsigned int samples, bool deferUpdate=false);
void setNumberOfHorizontalDivisions(unsigned int divisions);
void setNumberOfVerticalDivisions(unsigned int divisions);
void setDisplayLimits(uint traceNumber, TQRectF limits);
void setDisplayLimits(uint traceNumber, TQRectF limits, bool deferUpdate=false);
TQRectF displayLimits(uint traceNumber);
void setNumberOfTraces(uint traceNumber);
void setNumberOfCursors(uint traceNumber);
TQDoubleArray& samples(uint traceNumber);
void setSamples(uint traceNumber, TQDoubleArray&);
void setSamples(uint traceNumber, TQDoubleArray&, bool deferUpdate=false);
TQDoubleArray& positions(uint traceNumber);
void setPositions(uint traceNumber, TQDoubleArray&);
void setPositions(uint traceNumber, TQDoubleArray&, bool deferUpdate=false);
TQColor traceColor(uint traceNumber);
void setTraceColor(uint traceNumber, TQColor);
bool traceEnabled(uint traceNumber);
void setTraceEnabled(uint traceNumber, bool enabled, bool showText=true);
void setTraceEnabled(uint traceNumber, bool enabled, TextDisplayType showText=FullText, bool deferUpdate=false);
TQString traceName(uint traceNumber);
void setTraceName(uint traceNumber, TQString name);
void setTraceName(uint traceNumber, TQString name, bool deferUpdate=false);
TQString traceHorizontalUnits(uint traceNumber);
void setTraceHorizontalUnits(uint traceNumber, TQString units);
void setTraceHorizontalUnits(uint traceNumber, TQString units, bool deferUpdate=false);
TQString traceVerticalUnits(uint traceNumber);
void setTraceVerticalUnits(uint traceNumber, TQString units);
void setTraceVerticalUnits(uint traceNumber, TQString units, bool deferUpdate=false);
double cursorPosition(uint cursorNumber);
void setCursorPosition(uint cursorNumber, double position);
@ -240,13 +248,23 @@ class TraceWidget : public TQWidget
void setZoomCursorStartIndex(unsigned int index);
void showLeftTraceInfoArea(bool show);
void fitLeftTraceInfoArea(bool fit);
void setLeftTraceInfoAreaFitSpacing(int spacing);
void setMinimumPixelsPerHorizDiv(unsigned int pixels);
double traceOffset(uint traceNumber);
void setTraceOffset(uint traceNumber, double offset, bool deferUpdate);
double traceTextOffset(uint traceNumber);
void setTraceTextOffset(uint traceNumber, double offset, bool deferUpdate);
static TQString prettyFormat(double value, double rangeDetectValue, TQString baseUnits, unsigned int precision=3);
virtual TQSize sizeHint() const;
virtual TQSize minimumSizeHint() const;
public slots:
void setTraceOffset(uint traceNumber, double offset);
void setTraceTextOffset(uint traceNumber, double offset);
private slots:
void updateTraceText();
@ -287,6 +305,9 @@ class TraceWidget : public TQWidget
GraticuleWidget* m_graticuleWidget;
bool m_useAbsoluteHorizontalRange;
bool m_showLeftTraceInfoArea;
bool m_leftTraceInfoLabelsFit;
int m_leftTraceInfoAreaFitSpacing;
unsigned int m_minimumPixelsPerHorizDiv;
friend class GraticuleWidget;
friend class TraceData;

@ -8,19 +8,20 @@
module data_storage(
input clka,
input [7:0] dina,
input [(RAM_WIDTH-1):0] dina,
input [(RAM_ADDR_BITS-1):0] addra,
input wea,
output reg [7:0] douta);
output reg [(RAM_WIDTH-1):0] douta);
parameter RAM_ADDR_BITS = 14;
parameter RAM_WIDTH = 8;
// Xilinx specific directive
(* RAM_STYLE="BLOCK" *)
reg [RAM_WIDTH-1:0] data_storage_ram [(2**RAM_ADDR_BITS)-1:0];
// Registered
always @(posedge clka) begin
if (wea) begin
data_storage_ram[addra] <= dina;
@ -30,4 +31,12 @@ module data_storage(
end
end
// // Unregistered
// always @(posedge clka) begin
// if (wea) begin
// data_storage_ram[addra] <= dina;
// end
// end
// assign douta = data_storage_ram[addra];
endmodule

@ -23,22 +23,38 @@ module lcd_data_storage(
// Xilinx specific directive
(* RAM_STYLE="BLOCK" *)
reg [RAM_WIDTH-1:0] data_storage_ram [(2**5)-1:0];
reg [RAM_WIDTH-1:0] lcd_data_storage_ram [(2**5)-1:0];
// Registered
always @(posedge clka) begin
douta <= data_storage_ram[addra];
douta <= lcd_data_storage_ram[addra];
if (wea) begin
data_storage_ram[addra] <= dina;
lcd_data_storage_ram[addra] <= dina;
douta <= dina;
end
end
always @(posedge clkb) begin
doutb <= data_storage_ram[addrb];
doutb <= lcd_data_storage_ram[addrb];
if (web) begin
data_storage_ram[addrb] <= dinb;
lcd_data_storage_ram[addrb] <= dinb;
doutb <= dinb;
end
end
// // Unregistered
// always @(posedge clka) begin
// if (wea) begin
// lcd_data_storage_ram[addra] <= dina;
// end
// end
// assign douta = lcd_data_storage_ram[addra];
//
// always @(posedge clkb) begin
// if (web) begin
// lcd_data_storage_ram[addrb] <= dinb;
// end
// end
// assign doutb = lcd_data_storage_ram[addrb];
endmodule

@ -7,38 +7,63 @@
//////////////////////////////////////////////////////////////////////////////////
module logic_analyzer_data_storage(
input clka,
input clkb,
input [63:0] dina,
input [63:0] dinb,
input [10:0] addra,
input [10:0] addrb,
input clk,
input [(RAM_WIDTH-1):0] dina,
input [(RAM_WIDTH-1):0] dinb,
input [(RAM_ADDR_BITS-1):0] addra,
input [(RAM_ADDR_BITS-1):0] addrb,
input wea,
input web,
output reg [63:0] douta,
output reg [63:0] doutb);
output reg [(RAM_WIDTH-1):0] douta,
output reg [(RAM_WIDTH-1):0] doutb);
parameter RAM_ADDR_BITS = 11;
parameter RAM_WIDTH = 64;
// Xilinx specific directive
(* RAM_STYLE="BLOCK" *)
reg [RAM_WIDTH-1:0] data_storage_ram [(2**11)-1:0];
reg [RAM_WIDTH-1:0] logic_analyzer_data_storage_ram [(2**RAM_ADDR_BITS)-1:0];
// Initial RAM values for debugging
integer index;
initial begin
for (index = 0; index < ((2**RAM_ADDR_BITS)-1); index = index + 2) begin
logic_analyzer_data_storage_ram[index+0] = {(RAM_WIDTH/4){4'ha}};
logic_analyzer_data_storage_ram[index+1] = {(RAM_WIDTH/4){4'h5}};
end
end
// Registered
always @(posedge clka) begin
douta <= data_storage_ram[addra];
douta <= logic_analyzer_data_storage_ram[addra];
if (wea) begin
data_storage_ram[addra] <= dina;
logic_analyzer_data_storage_ram[addra] <= dina;
douta <= dina;
end
end
always @(posedge clkb) begin
doutb <= data_storage_ram[addrb];
doutb <= logic_analyzer_data_storage_ram[addrb];
if (web) begin
data_storage_ram[addrb] <= dinb;
logic_analyzer_data_storage_ram[addrb] <= dinb;
doutb <= dinb;
end
end
// // Unregistered
// always @(posedge clka) begin
// if (wea) begin
// logic_analyzer_data_storage_ram[addra] <= dina;
// end
// end
// assign douta = logic_analyzer_data_storage_ram[addra];
//
// always @(posedge clkb) begin
// if (web) begin
// logic_analyzer_data_storage_ram[addrb] <= dinb;
// end
// end
// assign doutb = logic_analyzer_data_storage_ram[addrb];
endmodule

@ -63,6 +63,10 @@ module main(
output userdevice_reset);
parameter RAM_ADDR_BITS = 15;
parameter CLKIN_PERIOD_NS = 10;
parameter LOGIC_ANALYZER_CLOCK_DIV = 2;
parameter LOGIC_ANALYZER_CLOCK_MULT = 2;
parameter LOGIC_ANALYZER_STEP = (CLKIN_PERIOD_NS*(LOGIC_ANALYZER_CLOCK_MULT/LOGIC_ANALYZER_CLOCK_DIV));
reg userdevice_reset_reg;
assign userdevice_reset = ~userdevice_reset_reg;
@ -70,6 +74,10 @@ module main(
assign host_serial_txd = userlogic_serial_rxd;
assign userlogic_serial_txd = host_serial_rxd;
wire main_clk;
wire main_clk_online;
main_clock_generator main_clock_generator(.clkin(clk), .clkout(main_clk), .online(main_clk_online));
reg [15:0] sixteen_bit_io_in;
reg [15:0] sixteen_bit_io_out;
reg [15:0] sixteen_bit_io_reg;
@ -77,7 +85,7 @@ module main(
assign sixteen_bit_io = (sixteen_bit_io_wen) ? sixteen_bit_io_out : 16'bz;
always @(posedge clk) begin
always @(posedge main_clk) begin
sixteen_bit_io_reg = sixteen_bit_io;
sixteen_bit_io_wen_reg = sixteen_bit_io_wen;
if (sixteen_bit_io_wen_reg == 1'b0) begin
@ -100,10 +108,10 @@ module main(
wire data_storage_clka;
reg [7:0] data_storage_dina;
reg [(RAM_ADDR_BITS-1):0] data_storage_addra;
reg data_storage_write_enable;
reg data_storage_write_enable = 1'b0;
wire [7:0] data_storage_data_out;
assign data_storage_clka = clk;
assign data_storage_clka = main_clk;
data_storage #(RAM_ADDR_BITS) data_storage(.clka(data_storage_clka), .dina(data_storage_dina), .addra(data_storage_addra),
.wea(data_storage_write_enable), .douta(data_storage_data_out));
@ -114,13 +122,13 @@ module main(
reg [7:0] lcd_data_storage_dinb;
reg [4:0] lcd_data_storage_addra;
reg [4:0] lcd_data_storage_addrb;
reg lcd_data_storage_wea;
reg lcd_data_storage_web;
reg lcd_data_storage_wea = 1'b0;
reg lcd_data_storage_web = 1'b0;
wire [7:0] lcd_data_storage_douta;
wire [7:0] lcd_data_storage_doutb;
assign lcd_data_storage_clka = clk;
assign lcd_data_storage_clkb = clk;
assign lcd_data_storage_clka = main_clk;
assign lcd_data_storage_clkb = main_clk;
lcd_data_storage lcd_data_storage(.clka(lcd_data_storage_clka), .clkb(lcd_data_storage_clkb),
.dina(lcd_data_storage_dina), .dinb(lcd_data_storage_dinb),
@ -129,7 +137,12 @@ module main(
.douta(lcd_data_storage_douta), .doutb(lcd_data_storage_doutb));
wire logic_analyzer_clk;
logic_analyzer_clock_generator logic_analyzer_clock_generator(.clkin(clk), .clkout(logic_analyzer_clk));
wire logic_analyzer_online;
//logic_analyzer_clock_generator #(LOGIC_ANALYZER_CLOCK_MULT, LOGIC_ANALYZER_CLOCK_DIV) logic_analyzer_clock_generator(.clkin(clk), .clkout(logic_analyzer_clk), .online(logic_analyzer_online));
// FIXME
// Work around block RAM problems
assign logic_analyzer_clk = main_clk;
assign logic_analyzer_online = 1'b1;
wire logic_analyzer_data_storage_clka;
wire logic_analyzer_data_storage_clkb;
@ -137,13 +150,13 @@ module main(
reg [63:0] logic_analyzer_data_storage_dinb;
reg [10:0] logic_analyzer_data_storage_addra;
reg [10:0] logic_analyzer_data_storage_addrb;
reg logic_analyzer_data_storage_wea;
reg logic_analyzer_data_storage_web;
reg logic_analyzer_data_storage_wea = 1'b0;
reg logic_analyzer_data_storage_web = 1'b0;
wire [63:0] logic_analyzer_data_storage_douta;
wire [63:0] logic_analyzer_data_storage_doutb;
assign logic_analyzer_data_storage_clka = clk;
assign logic_analyzer_data_storage_clkb = logic_analyzer_clk;
assign logic_analyzer_data_storage_clka = logic_analyzer_clk;
assign logic_analyzer_data_storage_clkb = main_clk;
logic_analyzer_data_storage logic_analyzer_data_storage(.clka(logic_analyzer_data_storage_clka), .clkb(logic_analyzer_data_storage_clkb),
.dina(logic_analyzer_data_storage_dina), .dinb(logic_analyzer_data_storage_dinb),
@ -163,7 +176,7 @@ module main(
reg clk_div_by_eight;
reg clk_div_by_sixteen;
always @(posedge clk) begin
always @(posedge main_clk) begin
clk_div_by_two = !clk_div_by_two;
end
@ -206,32 +219,32 @@ module main(
if (sseg_mux_latch[0] == 0) begin
led_display_bytes[0] = sseg_data_latch;
digit_blanker_1 = 0;
digit_blanker_2 = digit_blanker_2 + 1;
digit_blanker_3 = digit_blanker_3 + 1;
digit_blanker_4 = digit_blanker_4 + 1;
digit_blanker_2 = digit_blanker_2 + 1'b1;
digit_blanker_3 = digit_blanker_3 + 1'b1;
digit_blanker_4 = digit_blanker_4 + 1'b1;
end
if (sseg_mux_latch[1] == 0) begin
led_display_bytes[1] = sseg_data_latch;
digit_blanker_1 = digit_blanker_1 + 1;
digit_blanker_1 = digit_blanker_1 + 1'b1;
digit_blanker_2 = 0;
digit_blanker_3 = digit_blanker_3 + 1;
digit_blanker_4 = digit_blanker_4 + 1;
digit_blanker_3 = digit_blanker_3 + 1'b1;
digit_blanker_4 = digit_blanker_4 + 1'b1;
end
if (sseg_mux_latch[2] == 0) begin
led_display_bytes[2] = sseg_data_latch;
digit_blanker_1 = digit_blanker_1 + 1;
digit_blanker_2 = digit_blanker_2 + 1;
digit_blanker_1 = digit_blanker_1 + 1'b1;
digit_blanker_2 = digit_blanker_2 + 1'b1;
digit_blanker_3 = 0;
digit_blanker_4 = digit_blanker_4 + 1;
digit_blanker_4 = digit_blanker_4 + 1'b1;
end
if (sseg_mux_latch[3] == 0) begin
led_display_bytes[3] = sseg_data_latch;
digit_blanker_1 = digit_blanker_1 + 1;
digit_blanker_2 = digit_blanker_2 + 1;
digit_blanker_3 = digit_blanker_3 + 1;
digit_blanker_1 = digit_blanker_1 + 1'b1;
digit_blanker_2 = digit_blanker_2 + 1'b1;
digit_blanker_3 = digit_blanker_3 + 1'b1;
digit_blanker_4 = 0;
end
@ -258,39 +271,113 @@ module main(
//
//-----------------------------------------------------------------------------------
reg logic_analyzer_trigger;
reg logic_analyzer_trigger_prev;
reg [11:0] logic_analyzer_address_counter;
reg [32*8:0] logic_analyzer_signal_names [63:0];
initial begin
logic_analyzer_signal_names[0] <= "Four bit LEDs <0>\0";
logic_analyzer_signal_names[1] <= "Four bit LEDs <1>\0";
logic_analyzer_signal_names[2] <= "Four bit LEDs <2>\0";
logic_analyzer_signal_names[3] <= "Four bit LEDs <3>\0";
logic_analyzer_signal_names[4] <= "Four bit switches <0>\0";
logic_analyzer_signal_names[5] <= "Four bit switches <1>\0";
logic_analyzer_signal_names[6] <= "Four bit switches <2>\0";
logic_analyzer_signal_names[7] <= "Four bit switches <3>\0";
logic_analyzer_signal_names[8] <= "Eight bit LEDs <0>\0";
logic_analyzer_signal_names[9] <= "Eight bit LEDs <1>\0";
logic_analyzer_signal_names[10] <= "Eight bit LEDs <2>\0";
logic_analyzer_signal_names[11] <= "Eight bit LEDs <3>\0";
logic_analyzer_signal_names[12] <= "Eight bit LEDs <4>\0";
logic_analyzer_signal_names[13] <= "Eight bit LEDs <5>\0";
logic_analyzer_signal_names[14] <= "Eight bit LEDs <6>\0";
logic_analyzer_signal_names[15] <= "Eight bit LEDs <7>\0";
logic_analyzer_signal_names[16] <= "Eight bit switches <0>\0";
logic_analyzer_signal_names[17] <= "Eight bit switches <1>\0";
logic_analyzer_signal_names[18] <= "Eight bit switches <2>\0";
logic_analyzer_signal_names[19] <= "Eight bit switches <3>\0";
logic_analyzer_signal_names[20] <= "Eight bit switches <4>\0";
logic_analyzer_signal_names[21] <= "Eight bit switches <5>\0";
logic_analyzer_signal_names[22] <= "Eight bit switches <6>\0";
logic_analyzer_signal_names[23] <= "Eight bit switches <7>\0";
logic_analyzer_signal_names[24] <= "Seven-segment MUX <0>\0";
logic_analyzer_signal_names[25] <= "Seven-segment MUX <1>\0";
logic_analyzer_signal_names[26] <= "Seven-segment MUX <2>\0";
logic_analyzer_signal_names[27] <= "Seven-segment MUX <3>\0";
logic_analyzer_signal_names[28] <= "Seven-segment DATA <0>\0";
logic_analyzer_signal_names[29] <= "Seven-segment DATA <1>\0";
logic_analyzer_signal_names[30] <= "Seven-segment DATA <2>\0";
logic_analyzer_signal_names[31] <= "Seven-segment DATA <3>\0";
logic_analyzer_signal_names[32] <= "Seven-segment DATA <4>\0";
logic_analyzer_signal_names[33] <= "Seven-segment DATA <5>\0";
logic_analyzer_signal_names[34] <= "Seven-segment DATA <6>\0";
logic_analyzer_signal_names[35] <= "Seven-segment DATA <7>\0";
logic_analyzer_signal_names[36] <= "User memory DATA <0>\0";
logic_analyzer_signal_names[37] <= "User memory DATA <1>\0";
logic_analyzer_signal_names[38] <= "User memory DATA <2>\0";
logic_analyzer_signal_names[39] <= "User memory DATA <3>\0";
logic_analyzer_signal_names[40] <= "User memory DATA <4>\0";
logic_analyzer_signal_names[41] <= "User memory DATA <5>\0";
logic_analyzer_signal_names[42] <= "User memory DATA <6>\0";
logic_analyzer_signal_names[43] <= "User memory DATA <7>\0";
logic_analyzer_signal_names[44] <= "User memory ADDR <0>\0";
logic_analyzer_signal_names[45] <= "User memory ADDR <1>\0";
logic_analyzer_signal_names[46] <= "User memory ADDR <2>\0";
logic_analyzer_signal_names[47] <= "User memory ADDR <3>\0";
logic_analyzer_signal_names[48] <= "User memory ADDR <4>\0";
logic_analyzer_signal_names[49] <= "User memory ADDR <5>\0";
logic_analyzer_signal_names[50] <= "User memory ADDR <6>\0";
logic_analyzer_signal_names[51] <= "User memory ADDR <7>\0";
logic_analyzer_signal_names[52] <= "User memory ADDR <8>\0";
logic_analyzer_signal_names[53] <= "User memory ADDR <9>\0";
logic_analyzer_signal_names[54] <= "User memory ADDR <10>\0";
logic_analyzer_signal_names[55] <= "User memory ADDR <11>\0";
logic_analyzer_signal_names[56] <= "User memory ADDR <12>\0";
logic_analyzer_signal_names[57] <= "User memory ADDR <13>\0";
logic_analyzer_signal_names[58] <= "User memory ADDR <14>\0";
logic_analyzer_signal_names[59] <= "User memory ADDR <15>\0";
logic_analyzer_signal_names[60] <= "User memory WEN\0";
logic_analyzer_signal_names[61] <= "User memory WAIT\0";
logic_analyzer_signal_names[62] <= "GND REF\0";
logic_analyzer_signal_names[63] <= "User logic clock\0";
end
reg logic_analyzer_running = 1;
reg [15:0] logic_analyzer_timestep = LOGIC_ANALYZER_STEP;
reg [1:0] logic_analyzer_trigger = 2'b11;
reg [11:0] logic_analyzer_address_counter = 12'b100000000000;
always @(posedge logic_analyzer_clk) begin
// Trigger
logic_analyzer_trigger = ~userlogic_reset; // Trigger on userlogic_reset falling edge
if ((logic_analyzer_trigger == 1) && (logic_analyzer_trigger_prev == 0)) begin
logic_analyzer_trigger[1] = logic_analyzer_trigger[0];
logic_analyzer_trigger[0] = ~userlogic_reset; // Trigger on userlogic_reset falling edge
if ((logic_analyzer_running == 1) && (logic_analyzer_trigger[0] == 1) && (logic_analyzer_trigger[1] == 0)) begin
logic_analyzer_address_counter = 0;
end
// Data load
if (logic_analyzer_address_counter[11] == 1'b0) begin
logic_analyzer_data_storage_addrb = logic_analyzer_address_counter;
// Set up write address
logic_analyzer_data_storage_addra <= logic_analyzer_address_counter[10:0];
// Connect signals to logic analyzer
logic_analyzer_data_storage_dinb[3:0] = four_bit_leds;
logic_analyzer_data_storage_dinb[7:4] = four_bit_switches;
logic_analyzer_data_storage_dinb[15:8] = eight_bit_leds;
logic_analyzer_data_storage_dinb[23:16] = eight_bit_switches;
logic_analyzer_data_storage_dinb[27:24] = sseg_mux;
logic_analyzer_data_storage_dinb[35:28] = sseg_data;
logic_analyzer_data_storage_dinb[43:36] = usermem_data;
logic_analyzer_data_storage_dinb[59:44] = usermem_address;
logic_analyzer_data_storage_dinb[60] = usermem_wen;
logic_analyzer_data_storage_dinb[61] = usermem_wait;
logic_analyzer_data_storage_dinb[62] = 1'b0; // UNUSED
logic_analyzer_data_storage_dinb[63] = userlogic_clock;
logic_analyzer_data_storage_web = 1'b1;
logic_analyzer_address_counter = logic_analyzer_address_counter + 1;
logic_analyzer_data_storage_dina[3:0] <= four_bit_leds;
logic_analyzer_data_storage_dina[7:4] <= four_bit_switches;
logic_analyzer_data_storage_dina[15:8] <= eight_bit_leds;
logic_analyzer_data_storage_dina[23:16] <= eight_bit_switches;
logic_analyzer_data_storage_dina[27:24] <= sseg_mux;
logic_analyzer_data_storage_dina[35:28] <= sseg_data;
logic_analyzer_data_storage_dina[43:36] <= usermem_data;
logic_analyzer_data_storage_dina[59:44] <= usermem_address;
logic_analyzer_data_storage_dina[60] <= usermem_wen;
logic_analyzer_data_storage_dina[61] <= usermem_wait;
logic_analyzer_data_storage_dina[62] <= 1'b0; // UNUSED
logic_analyzer_data_storage_dina[63] <= userlogic_clock;
logic_analyzer_data_storage_wea <= 1'b1;
logic_analyzer_address_counter = logic_analyzer_address_counter + 1'b1;
end else begin
logic_analyzer_data_storage_addra <= 0;
logic_analyzer_data_storage_dina <= 0;
logic_analyzer_data_storage_wea <= 1'b0;
end
logic_analyzer_trigger_prev = logic_analyzer_trigger;
end
@ -310,40 +397,39 @@ module main(
reg [7:0] usermem_data_reg;
reg [RAM_ADDR_BITS:0] usermem_address_reg;
always @(posedge clk) begin
usermem_wen_reg = usermem_wen;
usermem_data_reg = usermem_data;
usermem_address_reg = usermem_address;
gpmc_advn_reg = gpmc_advn;
gpmc_oen_reg = gpmc_oen;
gpmc_wen_reg = gpmc_wen;
if (gpmc_wen_reg == 1'b0) begin
gpmc_data_reg = gpmc_data;
always @(posedge main_clk) begin
usermem_wen_reg <= usermem_wen;
usermem_data_reg <= usermem_data;
usermem_address_reg <= usermem_address;
gpmc_advn_reg <= gpmc_advn;
gpmc_oen_reg <= gpmc_oen;
gpmc_wen_reg <= gpmc_wen;
// wen and advn are both verified before executing any write operations to avoid momentary wen glitches corrupting memory contents
if ((gpmc_wen_reg == 1'b0) && (gpmc_advn_reg == 1'b0)) begin
gpmc_data_reg <= gpmc_data;
end
if (gpmc_advn_reg == 1'b0) begin
gpmc_address_reg = gpmc_address;
data_storage_write_enable = 1'b0;
lcd_data_storage_wea = 1'b0;
logic_analyzer_data_storage_wea = 1'b0;
gpmc_address_reg <= gpmc_address;
end
if (gpmc_wen_reg == 1'b1) begin
data_storage_write_enable = 1'b0;
lcd_data_storage_wea = 1'b0;
logic_analyzer_data_storage_wea = 1'b0;
data_storage_write_enable <= 1'b0;
lcd_data_storage_wea <= 1'b0;
logic_analyzer_data_storage_web <= 1'b0;
end
gpmc_data_driven <= ((~gpmc_oen_reg) && gpmc_wen_reg);
if (gpmc_address_reg[RAM_ADDR_BITS] == 1'b1) begin
// System memory access
usermem_wait = 1'b1;
if (gpmc_wen_reg == 1'b0) begin
data_storage_addra = gpmc_address_reg[(RAM_ADDR_BITS-1):0];
data_storage_dina = gpmc_data_reg;
data_storage_write_enable = 1'b1;
if ((gpmc_wen_reg == 1'b0) && (gpmc_advn_reg == 1'b0)) begin
data_storage_addra <= gpmc_address_reg[(RAM_ADDR_BITS-1):0];
data_storage_dina <= gpmc_data_reg;
data_storage_write_enable <= 1'b1;
end else begin
data_storage_addra = gpmc_address_reg[(RAM_ADDR_BITS-1):0];
data_storage_write_enable = 1'b0;
gpmc_data_out = data_storage_data_out;
data_storage_addra <= gpmc_address_reg[(RAM_ADDR_BITS-1):0];
data_storage_write_enable <= 1'b0;
gpmc_data_out <= data_storage_data_out;
end
end else begin
// User memory access
@ -354,30 +440,30 @@ module main(
// 0x20 - 0x3f: LCD data area
if (usermem_wen_reg == 1'b0) begin
if (usermem_address_reg[(RAM_ADDR_BITS-1):5] == 1) begin // Address range 0x20 - 0x3f
lcd_data_storage_addrb = usermem_address_reg[4:0];
lcd_data_storage_dinb = usermem_data_reg;
lcd_data_storage_web = 1'b1;
lcd_data_storage_addrb <= usermem_address_reg[4:0];
lcd_data_storage_dinb <= usermem_data_reg;
lcd_data_storage_web <= 1'b1;
end
end else begin
if (usermem_address_reg[(RAM_ADDR_BITS-1):5] == 1) begin // Address range 0x20 - 0x3f
lcd_data_storage_addrb = usermem_address_reg[4:0];
lcd_data_storage_web = 1'b0;
usermem_data_out = lcd_data_storage_doutb;
lcd_data_storage_addrb <= usermem_address_reg[4:0];
lcd_data_storage_web <= 1'b0;
usermem_data_out <= lcd_data_storage_doutb;
end else begin
// Default
usermem_data_out = 8'b00000000;
usermem_data_out <= 8'b00000000;
end
end
end else begin
// Client scratchpad memory area
if (usermem_wen_reg == 1'b0) begin
data_storage_addra = usermem_address_reg[(RAM_ADDR_BITS-1):0];
data_storage_dina = usermem_data_reg;
data_storage_write_enable = 1'b1;
data_storage_addra <= usermem_address_reg[(RAM_ADDR_BITS-1):0];
data_storage_dina <= usermem_data_reg;
data_storage_write_enable <= 1'b1;
end else begin
data_storage_addra = usermem_address_reg[(RAM_ADDR_BITS-1):0];
data_storage_write_enable = 1'b0;
usermem_data_out = data_storage_data_out;
data_storage_addra <= usermem_address_reg[(RAM_ADDR_BITS-1):0];
data_storage_write_enable <= 1'b0;
usermem_data_out <= data_storage_data_out;
end
end
@ -400,33 +486,55 @@ module main(
// 0x0c: User device control
// Bit 0: User logic reset
// Bit 1: User device reset
// 0x0d: Logic analyzer control
// Bit 0: Logic analyzer capture active
// Bit 7: Logic analyzer online (DCM locked) (read only)
// 0x0e: Logic analyzer timestep (ns) (upper 8 bits) (read only)
// 0x0f: Logic analyzer timestep (ns) (lower 8 bits) (read only)
// 0x20 - 0x3f: LCD data area
// 0x800 - 0xfff: Logic analyzer signal names area (read only)
// 0x4000 - 0x7fff: Logic analyzer data area (read only)
if (gpmc_wen_reg == 1'b0) begin
if ((gpmc_wen_reg == 1'b0) && (gpmc_advn_reg == 1'b0)) begin
if (gpmc_address_reg[(RAM_ADDR_BITS-1):5] == 1) begin // Address range 0x20 - 0x3f
lcd_data_storage_addra = gpmc_address_reg[4:0];
lcd_data_storage_dina = gpmc_data_reg;
lcd_data_storage_wea = 1'b1;
lcd_data_storage_addra <= gpmc_address_reg[4:0];
lcd_data_storage_dina <= gpmc_data_reg;
lcd_data_storage_wea <= 1'b1;
end else if (gpmc_address_reg[(RAM_ADDR_BITS-1):14] == 1) begin // Address range 0x4000 - 0x7fff
// FIXME
// Prevent incorrect operation of the block RAM by allowing the Port B write signal to be set under certain conditions
logic_analyzer_data_storage_addrb <= gpmc_address_reg[13:3];
logic_analyzer_data_storage_dinb[7:0] <= gpmc_data_reg;
logic_analyzer_data_storage_dinb[15:8] <= gpmc_data_reg;
logic_analyzer_data_storage_dinb[23:16] <= gpmc_data_reg;
logic_analyzer_data_storage_dinb[31:24] <= gpmc_data_reg;
logic_analyzer_data_storage_dinb[39:32] <= gpmc_data_reg;
logic_analyzer_data_storage_dinb[47:40] <= gpmc_data_reg;
logic_analyzer_data_storage_dinb[55:48] <= gpmc_data_reg;
logic_analyzer_data_storage_dinb[63:56] <= gpmc_data_reg;
logic_analyzer_data_storage_web <= 1'b1;
end else begin
case (gpmc_address_reg[(RAM_ADDR_BITS-1):0])
2: begin
four_bit_switches = gpmc_data_reg[3:0];
four_bit_switches <= gpmc_data_reg[3:0];
end
3: begin
eight_bit_switches = gpmc_data_reg;
eight_bit_switches <= gpmc_data_reg;
end
4: begin
sixteen_bit_io_out[15:8] = gpmc_data_reg;
sixteen_bit_io_out[15:8] <= gpmc_data_reg;
end
5: begin
sixteen_bit_io_out[7:0] = gpmc_data_reg;
sixteen_bit_io_out[7:0] <= gpmc_data_reg;
end
10: begin
userproc_start = gpmc_data_reg[0];
userproc_start <= gpmc_data_reg[0];
end
12: begin
userlogic_reset = gpmc_data_reg[0];
userdevice_reset_reg = gpmc_data_reg[1];
userlogic_reset <= gpmc_data_reg[0];
userdevice_reset_reg <= gpmc_data_reg[1];
end
13: begin
logic_analyzer_running <= gpmc_data_reg[0];
end
default: begin
// Do nothing
@ -435,92 +543,103 @@ module main(
end
end else begin
if (gpmc_address_reg[(RAM_ADDR_BITS-1):5] == 1) begin // Address range 0x20 - 0x3f
lcd_data_storage_addra = gpmc_address_reg[4:0];
lcd_data_storage_wea = 1'b0;
gpmc_data_out = lcd_data_storage_douta;
lcd_data_storage_addra <= gpmc_address_reg[4:0];
lcd_data_storage_wea <= 1'b0;
gpmc_data_out <= lcd_data_storage_douta;
end else if (gpmc_address_reg[(RAM_ADDR_BITS-1):11] == 1) begin // Address range 0x800 - 0xfff
gpmc_data_out <= logic_analyzer_signal_names[gpmc_address_reg[10:5]][(((32*8)-(gpmc_address_reg[4:0]*8))-1)-:8];
end else if (gpmc_address_reg[(RAM_ADDR_BITS-1):14] == 1) begin // Address range 0x4000 - 0x7fff
logic_analyzer_data_storage_addra = gpmc_address_reg[13:3];
logic_analyzer_data_storage_wea = 1'b0;
logic_analyzer_data_storage_addrb <= gpmc_address_reg[13:3];
logic_analyzer_data_storage_web <= 1'b0;
case (gpmc_address_reg[2:0])
0: begin
gpmc_data_out = logic_analyzer_data_storage_douta[7:0];
gpmc_data_out <= logic_analyzer_data_storage_doutb[63:56];
end
1: begin
gpmc_data_out = logic_analyzer_data_storage_douta[15:8];
gpmc_data_out <= logic_analyzer_data_storage_doutb[55:48];
end
2: begin
gpmc_data_out = logic_analyzer_data_storage_douta[23:16];
gpmc_data_out <= logic_analyzer_data_storage_doutb[47:40];
end
3: begin
gpmc_data_out = logic_analyzer_data_storage_douta[31:24];
gpmc_data_out <= logic_analyzer_data_storage_doutb[39:32];
end
4: begin
gpmc_data_out = logic_analyzer_data_storage_douta[39:32];
gpmc_data_out <= logic_analyzer_data_storage_doutb[31:24];
end
5: begin
gpmc_data_out = logic_analyzer_data_storage_douta[47:40];
gpmc_data_out <= logic_analyzer_data_storage_doutb[23:16];
end
6: begin
gpmc_data_out = logic_analyzer_data_storage_douta[55:48];
gpmc_data_out <= logic_analyzer_data_storage_doutb[15:8];
end
7: begin
gpmc_data_out = logic_analyzer_data_storage_douta[63:56];
gpmc_data_out <= logic_analyzer_data_storage_doutb[7:0];
end
endcase
end else begin
case (gpmc_address_reg[(RAM_ADDR_BITS-1):0])
0: begin
gpmc_data_out = 8'b01000010;
gpmc_data_out <= 8'b01000010;
end
1: begin
gpmc_data_out = 8'b00000001;
gpmc_data_out <= 8'b00000001;
end
2: begin
gpmc_data_out[7:4] = 0;
gpmc_data_out[3:0] = four_bit_leds;
gpmc_data_out[7:4] <= 0;
gpmc_data_out[3:0] <= four_bit_leds;
end
3: begin
gpmc_data_out = eight_bit_leds;
gpmc_data_out <= eight_bit_leds;
end
4: begin
gpmc_data_out = sixteen_bit_io_in[15:8];
gpmc_data_out <= sixteen_bit_io_in[15:8];
end
5: begin
gpmc_data_out = sixteen_bit_io_in[7:0];
gpmc_data_out <= sixteen_bit_io_in[7:0];
end
6: begin
gpmc_data_out = led_display_bytes[0];
gpmc_data_out <= led_display_bytes[0];
end
7: begin
gpmc_data_out = led_display_bytes[1];
gpmc_data_out <= led_display_bytes[1];
end
8: begin
gpmc_data_out = led_display_bytes[2];
gpmc_data_out <= led_display_bytes[2];
end
9: begin
gpmc_data_out = led_display_bytes[3];
gpmc_data_out <= led_display_bytes[3];
end
10: begin
gpmc_data_out[0] = userproc_start;
gpmc_data_out[1] = userproc_done;
gpmc_data_out[7:2] = 0;
gpmc_data_out[0] <= userproc_start;
gpmc_data_out[1] <= userproc_done;
gpmc_data_out[7:2] <= 0;
end
11: begin
gpmc_data_out = RAM_ADDR_BITS;
gpmc_data_out <= RAM_ADDR_BITS;
end
12: begin
gpmc_data_out[0] = userlogic_reset;
gpmc_data_out[1] = userdevice_reset_reg;
gpmc_data_out[7:1] = 0;
gpmc_data_out[0] <= userlogic_reset;
gpmc_data_out[1] <= userdevice_reset_reg;
gpmc_data_out[7:2] <= 0;
end
13: begin
gpmc_data_out[0] <= logic_analyzer_running;
gpmc_data_out[6:1] <= 0;
gpmc_data_out[7] <= logic_analyzer_online;
end
14: begin
gpmc_data_out <= logic_analyzer_timestep[15:8];
end
15: begin
gpmc_data_out <= logic_analyzer_timestep[7:0];
end
default: begin
gpmc_data_out = 0;
gpmc_data_out <= 0;
end
endcase
end
end
end
gpmc_data_driven = ((~gpmc_oen) && gpmc_wen);
end
endmodule

@ -0,0 +1,151 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
// uLab GPMC interface verification test bench
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//
// (c) 2014 Timothy Pearson
// Raptor Engineering
// http://www.raptorengineeringinc.com
//
//////////////////////////////////////////////////////////////////////////////////
module verification;
// Inputs
reg clk;
reg gpmc_advn;
reg gpmc_oen;
reg gpmc_wen;
reg [15:0] gpmc_address;
reg usermem_wen;
reg userproc_done;
reg userlogic_clock;
reg userlogic_serial_rxd;
reg host_serial_rxd;
reg [3:0] four_bit_leds;
reg [7:0] eight_bit_leds;
reg sixteen_bit_io_wen;
reg [3:0] sseg_mux;
reg [7:0] sseg_data;
// Outputs
wire usermem_wait;
wire userproc_start;
wire userlogic_reset;
wire userlogic_serial_txd;
wire host_serial_txd;
wire [3:0] four_bit_switches;
wire [7:0] eight_bit_switches;
wire sixteen_bit_io_mode;
wire userdevice_reset;
// Bidirs
wire [7:0] gpmc_data;
wire [7:0] usermem_data;
wire [15:0] usermem_address;
wire [15:0] sixteen_bit_io;
// Instantiate the Unit Under Test (UUT)
main uut (
.clk(clk),
.gpmc_advn(gpmc_advn),
.gpmc_oen(gpmc_oen),
.gpmc_wen(gpmc_wen),
.gpmc_data(gpmc_data),
.gpmc_address(gpmc_address),
.usermem_wen(usermem_wen),
.usermem_wait(usermem_wait),
.usermem_data(usermem_data),
.usermem_address(usermem_address),
.userproc_start(userproc_start),
.userproc_done(userproc_done),
.userlogic_reset(userlogic_reset),
.userlogic_clock(userlogic_clock),
.userlogic_serial_txd(userlogic_serial_txd),
.userlogic_serial_rxd(userlogic_serial_rxd),
.host_serial_txd(host_serial_txd),
.host_serial_rxd(host_serial_rxd),
.four_bit_leds(four_bit_leds),
.eight_bit_leds(eight_bit_leds),
.four_bit_switches(four_bit_switches),
.eight_bit_switches(eight_bit_switches),
.sixteen_bit_io(sixteen_bit_io),
.sixteen_bit_io_wen(sixteen_bit_io_wen),
.sixteen_bit_io_mode(sixteen_bit_io_mode),
.sseg_mux(sseg_mux),
.sseg_data(sseg_data),
.userdevice_reset(userdevice_reset)
);
reg gpmc_data_driven = 0;
reg [7:0] gpmc_data_out;
assign gpmc_data = (gpmc_data_driven) ? gpmc_data_out : 8'bz;
// Generate 100MHz clock
always begin
#5;
clk = !clk;
end
// Terminate test bench after specified time has elapsed
initial begin
#10000;
$finish;
end
// Test logic analyzer triggering and data acquisition
initial begin
// Initialize Inputs
clk = 0;
gpmc_advn = 0;
gpmc_oen = 0;
gpmc_wen = 0;
gpmc_address = 0;
usermem_wen = 0;
userproc_done = 0;
userlogic_clock = 0;
userlogic_serial_rxd = 0;
host_serial_rxd = 0;
four_bit_leds = 0;
eight_bit_leds = 0;
sixteen_bit_io_wen = 0;
sseg_mux = 0;
sseg_data = 0;
// Wait 100 ns for global reset to finish
#100;
// Send user logic reset signal to GPMC interface
gpmc_address = 16'h000c;
gpmc_data_out = 8'h01;
gpmc_data_driven = 1'b1;
gpmc_advn = 1'b0;
gpmc_wen = 1'b0;
#1000
gpmc_address = 16'h000c;
gpmc_data_out = 8'h00;
gpmc_data_driven = 1'b1;
gpmc_advn = 1'b0;
gpmc_wen = 1'b0;
#100
gpmc_data_driven = 1'b0;
gpmc_advn = 1'b1;
gpmc_wen = 1'b1;
end
endmodule

@ -0,0 +1,108 @@
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Wed Feb 26 21:06:18 2014
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:blk_mem_gen:7.3
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc6slx9
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3
# END Select
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=false
CSET axi_id_width=4
CSET axi_slave_type=Memory_Slave
CSET axi_type=AXI4_Full
CSET byte_size=9
CSET coe_file=no_coe_file_loaded
CSET collision_warnings=ALL
CSET component_name=lcd_data_storage
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET ecctype=No_ECC
CSET enable_32bit_address=false
CSET enable_a=Always_Enabled
CSET enable_b=Always_Enabled
CSET error_injection_type=Single_Bit_Error_Injection
CSET fill_remaining_memory_locations=false
CSET interface_type=Native
CSET load_init_file=false
CSET mem_file=no_Mem_file_loaded
CSET memory_type=True_Dual_Port_RAM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET port_a_clock=100
CSET port_a_enable_rate=100
CSET port_a_write_rate=50
CSET port_b_clock=100
CSET port_b_enable_rate=100
CSET port_b_write_rate=50
CSET primitive=8kx2
CSET read_width_a=8
CSET read_width_b=8
CSET register_porta_input_of_softecc=false
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=false
CSET register_portb_output_of_softecc=false
CSET remaining_memory_locations=0
CSET reset_memory_latch_a=false
CSET reset_memory_latch_b=false
CSET reset_priority_a=CE
CSET reset_priority_b=CE
CSET reset_type=SYNC
CSET softecc=false
CSET use_axi_id=false
CSET use_bram_block=Stand_Alone
CSET use_byte_write_enable=false
CSET use_error_injection_pins=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_rsta_pin=false
CSET use_rstb_pin=false
CSET write_depth_a=32
CSET write_width_a=8
CSET write_width_b=8
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-19T16:22:25Z
# END Extra information
GENERATE
# CRC: 6d3195aa

@ -0,0 +1,108 @@
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Wed Feb 26 10:22:39 2014
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:blk_mem_gen:7.3
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc6slx9
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3
# END Select
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=false
CSET axi_id_width=4
CSET axi_slave_type=Memory_Slave
CSET axi_type=AXI4_Full
CSET byte_size=9
CSET coe_file=no_coe_file_loaded
CSET collision_warnings=ALL
CSET component_name=logic_analyzer_data_storage
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET ecctype=No_ECC
CSET enable_32bit_address=false
CSET enable_a=Always_Enabled
CSET enable_b=Always_Enabled
CSET error_injection_type=Single_Bit_Error_Injection
CSET fill_remaining_memory_locations=true
CSET interface_type=Native
CSET load_init_file=false
CSET mem_file=no_Mem_file_loaded
CSET memory_type=True_Dual_Port_RAM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET port_a_clock=100
CSET port_a_enable_rate=100
CSET port_a_write_rate=50
CSET port_b_clock=100
CSET port_b_enable_rate=100
CSET port_b_write_rate=50
CSET primitive=8kx2
CSET read_width_a=64
CSET read_width_b=64
CSET register_porta_input_of_softecc=false
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=false
CSET register_portb_output_of_softecc=false
CSET remaining_memory_locations=AAAAAAAAAAAAAAAA
CSET reset_memory_latch_a=false
CSET reset_memory_latch_b=false
CSET reset_priority_a=CE
CSET reset_priority_b=CE
CSET reset_type=SYNC
CSET softecc=false
CSET use_axi_id=false
CSET use_bram_block=Stand_Alone
CSET use_byte_write_enable=false
CSET use_error_injection_pins=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_rsta_pin=false
CSET use_rstb_pin=false
CSET write_depth_a=2048
CSET write_width_a=64
CSET write_width_b=64
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-19T16:22:25Z
# END Extra information
GENERATE
# CRC: 7f171f5

@ -8,14 +8,23 @@
module logic_analyzer_clock_generator(
input clkin,
output clkout);
output clkout,
output online);
parameter LOGIC_ANALYZER_CLOCK_MULT = 2;
parameter LOGIC_ANALYZER_CLOCK_DIV = 2;
wire clk0;
wire clk2x;
reg reset;
wire clkfx;
reg reset = 1'b0;
wire locked;
wire [7:0] status;
assign clkout = clkfx;
assign clkout = clk0;
// assign clkout = clk2x;
// Only signal online if the DCM is locked and clkfx is toggling
assign online = locked & (~status[2]);
// DCM_SP: Digital Clock Manager
// Spartan-6
@ -24,8 +33,8 @@ module logic_analyzer_clock_generator(
DCM_SP #(
.CLKDV_DIVIDE(2.0), // CLKDV divide value
// (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16).
.CLKFX_DIVIDE(1), // Divide value on CLKFX outputs - D - (1-32)
.CLKFX_MULTIPLY(4), // Multiply value on CLKFX outputs - M - (2-32)
.CLKFX_DIVIDE(LOGIC_ANALYZER_CLOCK_DIV), // Divide value on CLKFX outputs - D - (1-32)
.CLKFX_MULTIPLY(LOGIC_ANALYZER_CLOCK_MULT), // Multiply value on CLKFX outputs - M - (2-32)
.CLKIN_DIVIDE_BY_2("FALSE"), // CLKIN divide by two (TRUE/FALSE)
.CLKIN_PERIOD(10.0), // Input clock period specified in nS
.CLKOUT_PHASE_SHIFT("NONE"), // Output phase shift (NONE, FIXED, VARIABLE)
@ -47,11 +56,11 @@ module logic_analyzer_clock_generator(
.CLK2X180(), // 1-bit output: 2X clock frequency, 180 degree clock output
.CLK90(), // 1-bit output: 90 degree clock output
.CLKDV(), // 1-bit output: Divided clock output
.CLKFX(), // 1-bit output: Digital Frequency Synthesizer output (DFS)
.CLKFX(clkfx), // 1-bit output: Digital Frequency Synthesizer output (DFS)
.CLKFX180(), // 1-bit output: 180 degree CLKFX output
.LOCKED(), // 1-bit output: DCM_SP Lock Output
.LOCKED(locked), // 1-bit output: DCM_SP Lock Output
.PSDONE(), // 1-bit output: Phase shift done output
.STATUS(), // 8-bit output: DCM_SP status output
.STATUS(status), // 8-bit output: DCM_SP status output
.CLKFB(clk0), // 1-bit input: Clock feedback input
.CLKIN(clkin), // 1-bit input: Clock input
.DSSEN(1'b0), // 1-bit input: Unsupported, specify to GND.
@ -65,12 +74,11 @@ module logic_analyzer_clock_generator(
reg [7:0] reset_counter = 8'b00000001;
always @(posedge clkin) begin
if (reset_counter[7] != 1'b1) begin
if (reset_counter[7] == 1'b0) begin
reset_counter = reset_counter << 1;
reset = 1'b1;
end else begin
reset = 1'b0;
end
end
endmodule

@ -1 +0,0 @@
../../../common/logic_analyzer_data_storage.v

@ -1,42 +1,84 @@
# (c) 2013 Timothy Pearson, Raptor Engineering
# (c) 2013-2014 Timothy Pearson, Raptor Engineering
# Released into the Public Domain
NET "clk" LOC = "V10" | IOSTANDARD = "LVCMOS33";
NET "clk" TNM_NET = clk;
TIMESPEC TS_clk = PERIOD "clk" 100000 KHz HIGH 50%;
NET "main_clk" TNM_NET = main_clk;
TIMESPEC TS_main_clk = PERIOD "main_clk" 100000 KHz HIGH 50%;
NET "gpmc_data<0>" OFFSET = OUT 8 ns AFTER "clk";
NET "gpmc_data<1>" OFFSET = OUT 8 ns AFTER "clk";
NET "gpmc_data<2>" OFFSET = OUT 8 ns AFTER "clk";
NET "gpmc_data<3>" OFFSET = OUT 8 ns AFTER "clk";
NET "gpmc_data<4>" OFFSET = OUT 8 ns AFTER "clk";
NET "gpmc_data<5>" OFFSET = OUT 8 ns AFTER "clk";
NET "gpmc_data<6>" OFFSET = OUT 8 ns AFTER "clk";
NET "gpmc_data<7>" OFFSET = OUT 8 ns AFTER "clk";
NET "gpmc_data<0>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
NET "gpmc_data<1>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
NET "gpmc_data<2>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
NET "gpmc_data<3>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
NET "gpmc_data<4>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
NET "gpmc_data<5>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
NET "gpmc_data<6>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
NET "gpmc_data<7>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
NET "gpmc_address<0>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
NET "gpmc_address<1>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
NET "gpmc_address<2>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
NET "gpmc_address<3>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
NET "gpmc_address<4>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
NET "gpmc_address<5>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
NET "gpmc_address<6>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
NET "gpmc_address<7>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
NET "gpmc_address<8>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
NET "gpmc_address<9>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
NET "gpmc_address<10>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
NET "gpmc_address<11>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
NET "gpmc_address<12>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
NET "gpmc_address<13>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
NET "gpmc_address<14>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
NET "gpmc_address<15>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
NET "gpmc_advn" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
NET "gpmc_oen" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
NET "gpmc_wen" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
#NET "serial_input" LOC = "T12" | IOSTANDARD = "LVCMOS33";
#NET "serial_output" LOC = "M10" | SLEW = FAST | IOSTANDARD = "LVCMOS33";
NET "gpmc_advn" LOC = "C5" | IOSTANDARD = "LVCMOS33";
NET "gpmc_oen" LOC = "A3" | IOSTANDARD = "LVCMOS33";
NET "gpmc_wen" LOC = "A5" | IOSTANDARD = "LVCMOS33";
NET "gpmc_data<0>" LOC = "A6" | SLEW = FAST | IOSTANDARD = "LVCMOS33";
NET "gpmc_data<1>" LOC = "C8" | SLEW = FAST | IOSTANDARD = "LVCMOS33";
NET "gpmc_data<2>" LOC = "C9" | SLEW = FAST | IOSTANDARD = "LVCMOS33";
NET "gpmc_data<3>" LOC = "A10" | SLEW = FAST | IOSTANDARD = "LVCMOS33";
NET "gpmc_data<4>" LOC = "C10" | SLEW = FAST | IOSTANDARD = "LVCMOS33";
NET "gpmc_data<5>" LOC = "D9" | SLEW = FAST | IOSTANDARD = "LVCMOS33";
NET "gpmc_data<6>" LOC = "D8" | SLEW = FAST | IOSTANDARD = "LVCMOS33";
NET "gpmc_data<7>" LOC = "B6" | SLEW = FAST | IOSTANDARD = "LVCMOS33";
NET "gpmc_address<0>" LOC = "A11" | IOSTANDARD = "LVCMOS33";
NET "gpmc_address<1>" LOC = "F9" | IOSTANDARD = "LVCMOS33";
NET "gpmc_address<2>" LOC = "A9" | IOSTANDARD = "LVCMOS33";
NET "gpmc_address<3>" LOC = "A8" | IOSTANDARD = "LVCMOS33";
NET "gpmc_address<4>" LOC = "A7" | IOSTANDARD = "LVCMOS33";
NET "gpmc_address<5>" LOC = "C6" | IOSTANDARD = "LVCMOS33";
NET "gpmc_address<6>" LOC = "A4" | IOSTANDARD = "LVCMOS33";
NET "gpmc_address<7>" LOC = "A2" | IOSTANDARD = "LVCMOS33";
NET "gpmc_address<8>" LOC = "B11" | IOSTANDARD = "LVCMOS33";
NET "gpmc_address<9>" LOC = "G9" | IOSTANDARD = "LVCMOS33";
NET "gpmc_address<10>" LOC = "B9" | IOSTANDARD = "LVCMOS33";
NET "gpmc_address<11>" LOC = "B8" | IOSTANDARD = "LVCMOS33";
NET "gpmc_address<12>" LOC = "C7" | IOSTANDARD = "LVCMOS33";
NET "gpmc_address<13>" LOC = "D6" | IOSTANDARD = "LVCMOS33";
NET "gpmc_address<14>" LOC = "B4" | IOSTANDARD = "LVCMOS33";
NET "gpmc_address<15>" LOC = "B2" | IOSTANDARD = "LVCMOS33";
NET "usermem_wen" LOC = "V16" | IOSTANDARD = "LVCMOS33";
NET "gpmc_advn" LOC = "C5" | FLOAT | IOSTANDARD = "LVCMOS33";
NET "gpmc_oen" LOC = "A3" | FLOAT | IOSTANDARD = "LVCMOS33";
NET "gpmc_wen" LOC = "A5" | FLOAT | IOSTANDARD = "LVCMOS33";
NET "gpmc_data<0>" LOC = "A6" | SLEW = FAST | FLOAT | IOSTANDARD = "LVCMOS33";
NET "gpmc_data<1>" LOC = "C8" | SLEW = FAST | FLOAT | IOSTANDARD = "LVCMOS33";
NET "gpmc_data<2>" LOC = "C9" | SLEW = FAST | FLOAT | IOSTANDARD = "LVCMOS33";
NET "gpmc_data<3>" LOC = "A10" | SLEW = FAST | FLOAT | IOSTANDARD = "LVCMOS33";
NET "gpmc_data<4>" LOC = "C10" | SLEW = FAST | FLOAT | IOSTANDARD = "LVCMOS33";
NET "gpmc_data<5>" LOC = "D9" | SLEW = FAST | FLOAT | IOSTANDARD = "LVCMOS33";
NET "gpmc_data<6>" LOC = "D8" | SLEW = FAST | FLOAT | IOSTANDARD = "LVCMOS33";
NET "gpmc_data<7>" LOC = "B6" | SLEW = FAST | FLOAT | IOSTANDARD = "LVCMOS33";
NET "gpmc_address<0>" LOC = "A11" | FLOAT | IOSTANDARD = "LVCMOS33";
NET "gpmc_address<1>" LOC = "F9" | FLOAT | IOSTANDARD = "LVCMOS33";
NET "gpmc_address<2>" LOC = "A9" | FLOAT | IOSTANDARD = "LVCMOS33";
NET "gpmc_address<3>" LOC = "A8" | FLOAT | IOSTANDARD = "LVCMOS33";
NET "gpmc_address<4>" LOC = "A7" | FLOAT | IOSTANDARD = "LVCMOS33";
NET "gpmc_address<5>" LOC = "C6" | FLOAT | IOSTANDARD = "LVCMOS33";
NET "gpmc_address<6>" LOC = "A4" | FLOAT | IOSTANDARD = "LVCMOS33";
NET "gpmc_address<7>" LOC = "A2" | FLOAT | IOSTANDARD = "LVCMOS33";
NET "gpmc_address<8>" LOC = "B11" | FLOAT | IOSTANDARD = "LVCMOS33";
NET "gpmc_address<9>" LOC = "G9" | FLOAT | IOSTANDARD = "LVCMOS33";
NET "gpmc_address<10>" LOC = "B9" | FLOAT | IOSTANDARD = "LVCMOS33";
NET "gpmc_address<11>" LOC = "B8" | FLOAT | IOSTANDARD = "LVCMOS33";
NET "gpmc_address<12>" LOC = "C7" | FLOAT | IOSTANDARD = "LVCMOS33";
NET "gpmc_address<13>" LOC = "D6" | FLOAT | IOSTANDARD = "LVCMOS33";
NET "gpmc_address<14>" LOC = "B4" | FLOAT | IOSTANDARD = "LVCMOS33";
NET "gpmc_address<15>" LOC = "B2" | FLOAT | IOSTANDARD = "LVCMOS33";
NET "usermem_wen" LOC = "V16" | PULLUP | IOSTANDARD = "LVCMOS33";
NET "usermem_wait" LOC = "T18" | SLEW = FAST | IOSTANDARD = "LVCMOS33";
NET "userproc_start" LOC = "K16" | SLEW = FAST | IOSTANDARD = "LVCMOS33";
NET "userproc_done" LOC = "L13" | IOSTANDARD = "LVCMOS33";

@ -0,0 +1,20 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
// (c) 2014 Timothy Pearson, Raptor Engineering
// Released into the Public Domain
//
//////////////////////////////////////////////////////////////////////////////////
module main_clock_generator(
input clkin,
output clkout,
output online);
assign online = 1'b1;
BUFG BUFG_inst (
.O(clkout), // 1-bit output: Clock buffer output
.I(clkin) // 1-bit input: Clock buffer input
);
endmodule

@ -16,28 +16,44 @@
<files>
<file xil_pn:name="data_storage.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="lcd_data_storage.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="main.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="logic_analyzer_data_storage.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="56"/>
<file xil_pn:name="logic_analyzer_clock_generator.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="main_clock_generator.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="logic_analyzer_clock_generator.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="56"/>
<file xil_pn:name="verification.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="58"/>
</file>
<file xil_pn:name="ipcore_dir/logic_analyzer_data_storage.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="83"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="ipcore_dir/lcd_data_storage.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="91"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="ipcore_dir/logic_analyzer_data_storage.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ipcore_dir/lcd_data_storage.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
<properties>
@ -151,7 +167,7 @@
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="uut" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|main" xil_pn:valueState="non-default"/>
@ -227,7 +243,7 @@
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="Standard" xil_pn:valueState="non-default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
@ -269,7 +285,7 @@
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
@ -281,27 +297,28 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/verification" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.verification" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="work.verification" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="work.verification" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="uut" xil_pn:valueState="non-default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="10000 ns" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.verification" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="work.verification" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.verification" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
@ -349,12 +366,12 @@
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|verification" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="ulab_debug_interface" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="Module|verification" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="Module|verification" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>

@ -20,16 +20,18 @@
#include "tqtrla.h"
#include <pwd.h>
#include <tqwidget.h>
#include <tqbuffer.h>
#include <kdialog.h>
#include <tdelocale.h>
#include <tdemessagebox.h>
// RAJA UNCOMMENT ME
//#define SERVER_TIMEOUT_MS 10000
// RAJA DEBUG ONLY
#define SERVER_TIMEOUT_MS 100000
#include <libtdeldap.h>
#define SERVER_TIMEOUT_MS 10000
#define FPGA_DATA_PROCESSING_TIMEOUT_MS 2500
namespace KParts
@ -106,6 +108,42 @@ namespace KParts
}
}
int RemoteInstrumentPart::getNewTicket() {
int ret = -1;
TQWidget* parentWidget = dynamic_cast<TQWidget*>(parent());
if (!parentWidget) {
return ret;
}
LDAPCredentials credentials;
KerberosTicketInfoList ticketList = LDAPManager::getKerberosTicketList();
if (ticketList.count() > 0) {
TQStringList princParts = TQStringList::split("@", ticketList[0].cachePrincipal);
credentials.username = princParts[0];
credentials.realm = princParts[1];
}
else {
struct passwd* pwd = getpwuid(geteuid());
if (pwd) {
credentials.username = TQString(pwd->pw_name);
}
}
int result = LDAPManager::getKerberosPassword(credentials, i18n("Please provide Kerberos credentials"), false, parentWidget);
if (result == KDialog::Accepted) {
TQString errorstring;
TQString service;
if (LDAPManager::obtainKerberosTicket(credentials, service, &errorstring) != 0) {
KMessageBox::error(parentWidget, i18n("<qt>Failed to obtain ticket<p>%1</qt>").arg(errorstring), i18n("Failed to obtain Kerberos ticket"));
}
else {
ret = 0;
}
}
return ret;
}
void RemoteInstrumentPart::setStatusMessage(const TQString& message) {
emit(statusMessageSet(message));
}
@ -147,9 +185,10 @@ namespace KParts
m_socket = new TDEKerberosClientSocket(this);
connect(m_socket, TQT_SIGNAL(statusMessageUpdated(const TQString&)), this, TQT_SLOT(setStatusMessage(const TQString&) ));
}
m_hostName = server;
m_socket->setServiceName("ulab");
m_socket->setServerFQDN(server);
m_socket->connectToHost(server, 4004);
m_socket->setServerFQDN(m_hostName);
m_socket->connectToHost(m_hostName, 4004);
// Finish connecting when appropriate
connToServerState = 0;
@ -221,12 +260,27 @@ namespace KParts
}
else {
if (m_socket->kerberosStatus() != TDEKerberosClientSocket::KerberosInUse) {
connToServerState = -1;
connToServerConnecting = false;
disconnectFromServer();
KMessageBox::error(0, i18n("<qt>Unable to establish Kerberos protocol with remote server<p>Please verify that you currently hold a valid Kerberos ticket</qt>"), i18n("Connection Failed"));
close();
return;
// Try to get a valid ticket
if (getNewTicket() == 0) {
// Retry connection if no obvious errors were detected
m_connectionTimer->stop();
if (m_socket) {
m_socket->clearPendingData();
m_socket->close();
delete m_socket;
m_socket = NULL;
}
connectToServer(m_hostName);
return;
}
else {
connToServerState = -1;
connToServerConnecting = false;
disconnectFromServer();
KMessageBox::error(0, i18n("<qt>Unable to establish Kerberos protocol with remote server<p>Please verify that you currently hold a valid Kerberos ticket</qt>"), i18n("Connection Failed"));
close();
return;
}
}
else {
connToServerState = 2;

@ -74,6 +74,9 @@ namespace KParts
void setMDIMainForm(KMdiMainFrm* form);
KMdiMainFrm* mdiMainForm();
private:
int getNewTicket();
private slots:
void finishConnectingToServer();
virtual void connectionFinishedCallback();
@ -102,6 +105,7 @@ namespace KParts
TQTimer *connToServerTimeoutTimer;
bool m_fixedSize;
KMdiMainFrm* m_mdiMainForm;
TQString m_hostName;
private:
RemoteInstrumentPartPrivate *d;

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