Timothy Pearson
6 years ago
parent
cd7e1ea3b8
commit
f8f6ee88d8
@ -0,0 +1,123 @@
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# This file is part of the Universal Laboratory (uLab)
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#
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# © 2017 - 2019 Raptor Engineering, LLC
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# All Rights Reserved
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#
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# Licensed under the terms of the AGPL v3
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MAX_FPGA_ROUTE_PASSES = 100
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SOURCE_FILES = main.v
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# Default seed
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#ARACHNE_PNR_SEED = 1
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# Selected seed from fastest placement search
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# NOTE: Must be updated every time the Verilog source is modified, no matter how trivially!
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# Does not need to be updated if firmware program (C) sources are modified
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# 0 automatically uses the best placement result
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ARACHNE_PNR_SEED = 0
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#ARACHNE_PNR_SEED = 1
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YOSYS_ICE40_SIM_LIB = $(shell yosys-config --datdir/ice40/cells_sim.v)
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.PRECIOUS: guest_fpga_%.int
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guest_fpga_%.tmg: guest_fpga_%.int guest_fpga.pcf
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echo "Total path delay: inf ns (0.0 MHz)" > $@
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-icetime -tmd hx8k -p guest_fpga.pcf -P ct256 $< > $@ 2>&1
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guest_fpga_%.int: guest_fpga.blif guest_fpga.pcf
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echo "" > $@
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-arachne-pnr -s $* -d 8k -P ct256 -m $(MAX_FPGA_ROUTE_PASSES) -p guest_fpga.pcf $< -o $@
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guest_fpga.int: guest_fpga_1.tmg guest_fpga_2.tmg guest_fpga_3.tmg guest_fpga_4.tmg guest_fpga_5.tmg guest_fpga_6.tmg guest_fpga_7.tmg guest_fpga_8.tmg guest_fpga_9.tmg \
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guest_fpga_10.tmg guest_fpga_11.tmg guest_fpga_12.tmg guest_fpga_13.tmg guest_fpga_14.tmg guest_fpga_15.tmg guest_fpga_16.tmg guest_fpga_17.tmg guest_fpga_18.tmg guest_fpga_19.tmg \
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guest_fpga_20.tmg guest_fpga_21.tmg guest_fpga_22.tmg guest_fpga_23.tmg guest_fpga_24.tmg guest_fpga_25.tmg guest_fpga_26.tmg guest_fpga_27.tmg guest_fpga_28.tmg guest_fpga_29.tmg \
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guest_fpga_30.tmg guest_fpga_31.tmg guest_fpga_32.tmg guest_fpga_33.tmg guest_fpga_34.tmg guest_fpga_35.tmg guest_fpga_36.tmg guest_fpga_37.tmg guest_fpga_38.tmg guest_fpga_39.tmg \
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guest_fpga_40.tmg guest_fpga_41.tmg guest_fpga_42.tmg guest_fpga_43.tmg guest_fpga_44.tmg guest_fpga_45.tmg guest_fpga_46.tmg guest_fpga_47.tmg guest_fpga_48.tmg guest_fpga_49.tmg \
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guest_fpga_50.tmg guest_fpga_51.tmg guest_fpga_52.tmg guest_fpga_53.tmg guest_fpga_54.tmg guest_fpga_55.tmg guest_fpga_56.tmg guest_fpga_57.tmg guest_fpga_58.tmg guest_fpga_59.tmg \
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guest_fpga_60.tmg guest_fpga_61.tmg guest_fpga_62.tmg guest_fpga_63.tmg guest_fpga_64.tmg
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BEST_TRIAL=0; \
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BEST_TRIAL_RESULT=0; \
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for trial in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64; do \
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CURRENT_TRIAL_RESULT=$$(cat guest_fpga_$${trial}.tmg | grep "Total path delay" | awk '{print $$6}' | sed 's/(//g'); \
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if [ "$$CURRENT_TRIAL_RESULT" != "" ]; then \
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echo "guest_fpga_$${trial}.tmg : $$CURRENT_TRIAL_RESULT"; \
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COMPARISON_RESULT=$$(echo "$$CURRENT_TRIAL_RESULT > $$BEST_TRIAL_RESULT" | bc -l); \
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if [ $$COMPARISON_RESULT -eq 1 ]; then \
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BEST_TRIAL=guest_fpga_$${trial}.tmg; \
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BEST_TRIAL_RESULT=$$CURRENT_TRIAL_RESULT; \
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fi; \
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fi; \
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done; \
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if [ "$$BEST_TRIAL_RESULT" -eq "0" ]; then \
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echo "Unable to determine fastest result. Selecting first run...."; \
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BEST_TRIAL=guest_fpga_1.tmg; \
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BEST_TRIAL_RESULT=0; \
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fi; \
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echo "Fastest result: $$BEST_TRIAL : $$BEST_TRIAL_RESULT"; \
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cp `echo $$BEST_TRIAL | sed 's/\.tmg/\.int/g'` guest_fpga.int; \
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cp $$BEST_TRIAL guest_fpga.tmg
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ifneq ($(ARACHNE_PNR_SEED),0)
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cp guest_fpga_$(ARACHNE_PNR_SEED).int guest_fpga.int
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cp guest_fpga_$(ARACHNE_PNR_SEED).tmg guest_fpga.tmg
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endif
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cat guest_fpga.tmg
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guest_fpga.ex: guest_fpga.int
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icebox_explain guest_fpga.int > guest_fpga.ex
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guest_fpga.blif: $(SOURCE_FILES)
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yosys -l yosys.log -q -p "synth_ice40 -top guest_fpga_top -blif guest_fpga.blif" $(SOURCE_FILES)
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guest_fpga.bin: guest_fpga.int
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icepack guest_fpga.int guest_fpga.bin
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blank.rom:
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dd if=/dev/zero ibs=1k count=256 | tr "\000" "\377" > blank.rom
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guest_fpga.rom: blank.rom guest_fpga.bin
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cp blank.rom guest_fpga.rom
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dd if=guest_fpga.bin of=guest_fpga.rom conv=notrunc
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guest_fpga_test.vcd: $(SOURCE_FILES) testbench.v
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rm -f guest_fpga_sim
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rm -f guest_fpga.vcd
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/usr/bin/iverilog -DSIMULATION -o guest_fpga_sim $(SOURCE_FILES) testbench.v
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./guest_fpga_sim
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simulate: guest_fpga_test.vcd
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simulate_view: guest_fpga_test.vcd
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gtkwave guest_fpga_test.vcd
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all: guest_fpga.rom
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dump_toolchain_info:
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-@echo "================================================================================"
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-@echo "Base system:\t"
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-@echo -n "Architecture:\t"
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-@uname -m 2>/dev/null
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-@echo -n "gcc:\t\t"
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-@gcc -dumpversion 2>/dev/null
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-@echo -n "clang:\t\t"
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-@clang --version 2>/dev/null | head -n 1
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-@echo "\nFPGA toolchain:"
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-@echo -n "Icarus verilog:\t"
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-@iverilog -V 2>/dev/null | head -n 1
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-@echo -n "Yosys:\t\t"
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-@yosys -V 2>/dev/null
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-@echo -n "arachne-pnr:\t"
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-@arachne-pnr -v 2>/dev/null
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-@echo "================================================================================"
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test: guest_fpga.bin
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iceprog -S guest_fpga.bin
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flash: guest_fpga.bin
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iceprog guest_fpga.bin
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clean:
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rm -f guest_fpga.blif guest_fpga.ex guest_fpga.int guest_fpga.tmg guest_fpga_*.int guest_fpga_*.tmg guest_fpga.bin yosys.log
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@ -0,0 +1,106 @@
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# This file is part of the Universal Laboratory (uLab)
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#
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# © 2017 - 2019 Raptor Engineering, LLC
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# All Rights Reserved
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#
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# Licensed under the terms of the AGPL v3
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# Main system clock
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set_io clk J3
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# Guest FPGA interface
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set_io reset A16
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set_io four_bit_output[3] C16
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set_io four_bit_output[2] D16
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set_io four_bit_output[1] E16
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set_io four_bit_output[0] F16
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set_io four_bit_input[3] B16
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set_io four_bit_input[2] D14
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set_io four_bit_input[1] D15
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set_io four_bit_input[0] E14
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set_io eight_bit_output[7] G16
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set_io eight_bit_output[6] H16
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set_io eight_bit_output[5] J15
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set_io eight_bit_output[4] G14
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set_io eight_bit_output[3] K14
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set_io eight_bit_output[2] K15
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set_io eight_bit_output[1] M16
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set_io eight_bit_output[0] N16
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set_io eight_bit_input[7] F15
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set_io eight_bit_input[6] G15
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set_io eight_bit_input[5] H14
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set_io eight_bit_input[4] F14
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set_io eight_bit_input[3] J14
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set_io eight_bit_input[2] K16
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set_io eight_bit_input[1] L16
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set_io eight_bit_input[0] M15
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set_io sixteen_bit_output[15] B1
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set_io sixteen_bit_output[14] C1
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set_io sixteen_bit_output[13] D1
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set_io sixteen_bit_output[12] E2
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set_io sixteen_bit_output[11] F2
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set_io sixteen_bit_output[10] G2
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set_io sixteen_bit_output[9] H2
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set_io sixteen_bit_output[8] J2
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set_io sixteen_bit_output[7] K3
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set_io sixteen_bit_output[6] L3
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set_io sixteen_bit_output[5] M2
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set_io sixteen_bit_output[4] N3
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set_io sixteen_bit_output[3] P1
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set_io sixteen_bit_output[2] B12
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set_io sixteen_bit_output[1] B13
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set_io sixteen_bit_output[0] A15
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set_io sixteen_bit_input[15] B2
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set_io sixteen_bit_input[14] C2
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set_io sixteen_bit_input[13] D2
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set_io sixteen_bit_input[12] F1
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set_io sixteen_bit_input[11] G1
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set_io sixteen_bit_input[10] H1
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set_io sixteen_bit_input[9] R1
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set_io sixteen_bit_input[8] J1
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set_io sixteen_bit_input[7] K1
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set_io sixteen_bit_input[6] L1
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set_io sixteen_bit_input[5] M1
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set_io sixteen_bit_input[4] N2
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set_io sixteen_bit_input[3] P2
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set_io sixteen_bit_input[2] B11
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set_io sixteen_bit_input[1] B14
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set_io sixteen_bit_input[0] B15
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set_io lcd_data_in_address[5] T11
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set_io lcd_data_in_address[4] N10
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set_io lcd_data_in_address[3] N12
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set_io lcd_data_in_address[2] T13
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set_io lcd_data_in_address[1] T15
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set_io lcd_data_in_address[0] R16
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set_io lcd_data_in_data[7] R6
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set_io lcd_data_in_data[6] T8
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set_io lcd_data_in_data[5] R9
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set_io lcd_data_in_data[4] P9
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set_io lcd_data_in_data[3] R10
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set_io lcd_data_in_data[2] P10
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set_io lcd_data_in_data[1] M11
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set_io lcd_data_in_data[0] P13
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set_io lcd_data_in_enable T14
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set_io led_segment_bus[7] T1
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set_io led_segment_bus[6] R2
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set_io led_segment_bus[5] R3
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set_io led_segment_bus[4] T5
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set_io led_segment_bus[3] T6
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set_io led_segment_bus[2] T7
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set_io led_segment_bus[1] P8
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set_io led_segment_bus[0] T10
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set_io led_digit_select[3] T2
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set_io led_digit_select[2] T3
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set_io led_digit_select[1] R4
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set_io led_digit_select[0] R5
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@ -0,0 +1,104 @@
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// This file is part of the Universal Laboratory (uLab)
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//
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// © 2007 - 2019 Raptor Engineering, LLC
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// All Rights Reserved
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//
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// Licensed under the terms of the AGPL v3
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module guest_fpga_top(clk, reset, four_bit_input, four_bit_output, eight_bit_input, eight_bit_output, sixteen_bit_input, sixteen_bit_output, lcd_data_in_address, lcd_data_in_data, lcd_data_in_enable, led_segment_bus, led_digit_select);
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input clk;
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input reset;
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input [3:0] four_bit_input;
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output reg [3:0] four_bit_output;
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input [7:0] eight_bit_input;
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output reg [7:0] eight_bit_output;
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input [15:0] sixteen_bit_input;
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output reg [15:0] sixteen_bit_output;
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output reg [5:0] lcd_data_in_address;
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output reg [7:0] lcd_data_in_data;
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output reg lcd_data_in_enable;
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output reg [7:0] led_segment_bus;
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output reg [3:0] led_digit_select;
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reg [7:0] lcd_sample_counter = 48; // Create a sample LCD display counter register
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reg [31:0] lcd_character_change_timer = 0; // Wait a certain number of cycles before loading a new character
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reg [5:0] lcd_current_character = 0; // The current character's address
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always @(posedge clk) begin
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four_bit_output = four_bit_input; // Loopback
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eight_bit_output = eight_bit_input[3:0] + eight_bit_input[7:4]; // Sample adder
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sixteen_bit_output = sixteen_bit_input[15:8] * sixteen_bit_input[7:0]; // Sample multiplier
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// Sample LCD display routine
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lcd_data_in_address = lcd_current_character; // Character location on the LCD display
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lcd_data_in_data = lcd_sample_counter; // Character code to display
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lcd_data_in_enable = 1; // Enable data transmission
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// Cycle through all character positions
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lcd_current_character = lcd_current_character + 1;
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if (lcd_current_character > 31) begin
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lcd_current_character = 16;
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end
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// Cycle through the numbers 0 to 9 at one second intervals
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lcd_character_change_timer = lcd_character_change_timer + 1;
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if (lcd_character_change_timer > 6000000) begin // Wait one second in between character changes
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lcd_character_change_timer = 0;
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lcd_sample_counter = lcd_sample_counter + 1;
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if (lcd_sample_counter > 57) begin // Character code for the digit 9
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lcd_sample_counter = 48; // Character code for the digit 0
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end
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end
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end
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// 7-segment LED display driver clock generator
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reg sseg_clock;
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reg [4:0] sseg_clock_counter;
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always @(posedge clk) begin
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sseg_clock_counter = sseg_clock_counter + 1;
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if (sseg_clock_counter > 16) begin
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sseg_clock_counter = 0;
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sseg_clock = ~sseg_clock;
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end
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end
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// 7-segment LED display driver
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// led_segment_bus and led_digit_select are active low
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// The bit sequence, MSB to LSB, is dp a b c d e f g
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// Segment letters are taken from ug130.pdf page 15
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// 0: 8'b10000001
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// 1: 8'b11001111
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// 2: 8'b10010010
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// 3: 8'b10000110
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reg [2:0] current_anode;
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always @(posedge sseg_clock) begin
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current_anode = current_anode + 1;
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if (current_anode > 3) begin
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current_anode = 0;
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end
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case (current_anode)
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0: begin
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led_digit_select = 4'b1110;
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led_segment_bus = 8'b10000001;
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end
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1: begin
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led_digit_select = 4'b1101;
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led_segment_bus = 8'b11001111;
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end
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2: begin
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led_digit_select = 4'b1011;
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led_segment_bus = 8'b10010010;
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end
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3: begin
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led_digit_select = 4'b0111;
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led_segment_bus = 8'b10000110;
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end
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endcase
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end
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endmodule
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