Add user logic reset support to serial version of FPGA control interface

fpga/serial/common/remote_access.v

@@ -23,6 +23,7 @@
 
 module remote_access(
 	input main_fifty_clock,				// 50MHz clock in
+	output user_logic_reset,			// Active high user logic reset out
 	input [3:0] remote_access_4_bit_output,		// 4 bit output from the user program to remote access client
 	output [3:0] remote_access_4_bit_input,		// 4 bit input from the remote access client to user program
 	input [7:0] remote_access_8_bit_output,		// 8 bit output from the user program to remote access client
@@ -66,6 +67,8 @@ module remote_access(
 `ifndef SYSTEM_HAS_SRAM
 	reg sram_processing_done = 1'b1;
 `endif
+
+	reg user_logic_reset_reg = 1'b0;
 	
 	reg [7:0] remote_access_4_bit_input_reg;
 	reg [7:0] remote_access_8_bit_input_reg;
@@ -79,6 +82,7 @@ module remote_access(
 	reg sram_available_reg;
 	reg startup_needed = 1;
 	
+	assign user_logic_reset = user_logic_reset_reg;
 	assign remote_access_4_bit_input = remote_access_4_bit_input_reg[3:0];
 	assign remote_access_8_bit_input = remote_access_8_bit_input_reg;
 	assign remote_access_16_bit_input = remote_access_16_bit_input_reg;
@@ -622,6 +626,9 @@ module remote_access(
 		end
 	
 		if (RxD_data_ready == 1) begin
+			// Release user logic reset if set on previous serial receive cycle
+			user_logic_reset_reg = 1'b0;
+
 			if (serial_character_received == 0) begin
 				serial_rx_data_reg = RxD_data;
 				serial_rx_strobe_reg = 1;		// Signal new data...
@@ -757,6 +764,11 @@ module remote_access(
 									// Transmit the DSP RAM size
 									transmit_dsp_ram_size = 1;
 								end
+
+								if (serial_command_buffer == 82) begin
+									// Strobe user logic reset
+									user_logic_reset_reg = 1'b1;
+								end
 							end else begin
 								if (next_byte_is_command == 1) begin
 									// The previous byte was the command--now load in the data!

fpga/serial/lattice/eb85/control_fpga.pcf

@@ -19,6 +19,8 @@ set_io led_bank[1] B4
 set_io led_bank[0] B5
 
 # Guest FPGA interface
+set_io guest_logic_reset A16
+
 set_io four_bit_output[3] C16
 set_io four_bit_output[2] D16
 set_io four_bit_output[1] E16

fpga/serial/lattice/eb85/main.v

@@ -11,6 +11,8 @@ module control_fpga_top
 		input wire main_12_mhz_clock,
 
 		// Guest FPGA interface
+		output wire guest_logic_reset,		// Active high guest logic reset signal
+
 		input wire [3:0] four_bit_output,	// Output from the user program to the remote access module
 		output wire [3:0] four_bit_input,	// Input to the user program from the remote access module
 		input wire [7:0] eight_bit_output,	// Output from the user program to the remote access module
@@ -87,7 +89,7 @@ module control_fpga_top
 	assign lcd_data_in_data = 8'b0;		// Disable LCD I/O for now
 
 	// Instantiate main remote access module
-	remote_access #(RAM_ADDR_BITS) remote_access(.main_fifty_clock(main_50_mhz_clock), .remote_access_4_bit_output(four_bit_output),
+	remote_access #(RAM_ADDR_BITS) remote_access(.main_fifty_clock(main_50_mhz_clock), .user_logic_reset(guest_logic_reset), .remote_access_4_bit_output(four_bit_output),
 		.remote_access_4_bit_input(four_bit_input), .remote_access_8_bit_output(eight_bit_output),
 		.remote_access_8_bit_input(eight_bit_input), .remote_access_16_bit_output(sixteen_bit_output),
 		.remote_access_16_bit_input(sixteen_bit_input),