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Allow data processing RAM size to be configured by changing a Verilog parameter on the FPGA side

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master
Timothy Pearson 11 years ago
parent 8faa3da109
commit f27e0f0184
6 changed files with 90 additions and 35 deletions
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4
clients/tde/src/part/fpgaview/layout.ui
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@ -706,7 +706,7 @@
<cstring>groupInputImage</cstring>
</property>
<property name="title">
<string>Input Image (128x128):</string>
<string>Input Image:</string>
</property>
<grid>
<property name="name">
@ -767,7 +767,7 @@
<cstring>groupOutputImage</cstring>
</property>
<property name="title">
<string>Output Image (128x128):</string>
<string>Output Image:</string>
</property>
<grid>
<property name="name">

41
clients/tde/src/part/fpgaview/part.cpp
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@ -47,6 +47,7 @@
#include <tqprogressbar.h>
#include <unistd.h> //access()
#include <stdint.h>
#include <math.h>
#include <tqpainter.h>
@ -589,7 +590,8 @@ FPGAViewPart::FPGAViewPart(TQWidget *parentWidget, const char *widgetName, TQObj
m_commHandlerState(0), m_commHandlerMode(0), m_commHandlerNextState(0), m_commHandlerNextMode(0), m_connectionActiveAndValid(false), m_tickerState(0), m_remoteInputModeEnabled(false), m_4bitInputValue(0), m_4bitOutputValue(0),
m_8bitInputValue(0), m_8bitOutputValue(0), m_16bitInputValue(0), m_16bitOutputValue(0), m_7segDigit3OutputValue(0xff),
m_7segDigit2OutputValue(0xff), m_7segDigit1OutputValue(0xff), m_7segDigit0OutputValue(0xff),
m_batchOutputFile(NULL), m_dataOutputFile(NULL), m_dataMemorySize(16384),
m_batchOutputFile(NULL), m_dataOutputFile(NULL), m_dataMemorySize(16384), m_dataMemorySizePrev(0),
m_dataMemoryImageWidth(128), m_dataMemoryImageHeight(128),
m_inputImageViewer(NULL), m_outputImageViewer(NULL)
{
// Initialize important base class variables
@ -989,12 +991,12 @@ void FPGAViewPart::processLockouts() {
if (!m_inputImageViewer) {
m_inputImageViewer = new ImageViewerWindow(i18n("Remote FPGA Input Image"));
mdiMainForm()->addWindow(m_inputImageViewer);
m_inputImageViewer->resize(m_base->ImageInputLabel->size());
m_inputImageViewer->resize(m_dataMemoryImageWidth, m_dataMemoryImageHeight);
}
if (!m_outputImageViewer) {
m_outputImageViewer = new ImageViewerWindow(i18n("Remote FPGA Output Image"));
mdiMainForm()->addWindow(m_outputImageViewer);
m_outputImageViewer->resize(m_base->ImageOutputLabel->size());
m_outputImageViewer->resize(m_dataMemoryImageWidth, m_dataMemoryImageHeight);
}
}
@ -1191,6 +1193,21 @@ void FPGAViewPart::receiveInputStatesFromRemoteFPGA() {
m_remoteInputModeEnabled = true;
}
// DSP RAM size
m_socket->readBlock(data, 1);
m_dataMemorySize = pow(2, data[0]);
if (m_dataMemorySize != m_dataMemorySizePrev) {
unsigned int newSize = round(sqrt(m_dataMemorySize));
m_dataMemoryImageWidth = newSize;
m_dataMemoryImageHeight = newSize;
m_base->groupInputImage->setTitle(TQString("Input Image (%1x%2):").arg(m_dataMemoryImageWidth).arg(m_dataMemoryImageHeight));
m_base->groupOutputImage->setTitle(TQString("Output Image (%1x%2):").arg(m_dataMemoryImageWidth).arg(m_dataMemoryImageHeight));
m_inputImageViewer->resize(m_dataMemoryImageWidth, m_dataMemoryImageHeight);
m_outputImageViewer->resize(m_dataMemoryImageWidth, m_dataMemoryImageHeight);
m_dataMemorySizePrev = m_dataMemorySize;
}
// 4-bit outputs
m_socket->readBlock(data, 1);
m_4bitOutputValue = data[0];
@ -1260,8 +1277,8 @@ void FPGAViewPart::updateDisplay() {
break;
case 1:
// Get all data
if (m_socket->bytesAvailable() >= 41) {
if (m_socket->bytesAvailable() == 41) {
if (m_socket->bytesAvailable() >= 42) {
if (m_socket->bytesAvailable() == 42) {
// Process the received data packet
receiveInputStatesFromRemoteFPGA();
@ -1392,8 +1409,8 @@ void FPGAViewPart::updateDisplay() {
}
else if (m_commHandlerState == 2) {
// Get all data
if (m_socket->bytesAvailable() >= 41) {
if (m_socket->bytesAvailable() == 41) {
if (m_socket->bytesAvailable() >= 42) {
if (m_socket->bytesAvailable() == 42) {
TQString line;
// Process the received data packet
@ -1483,7 +1500,10 @@ void FPGAViewPart::updateDisplay() {
// Show image in GUI
TQPixmap inputImagePixmap(displayImage);
m_base->ImageInputLabel->setPixmap(inputImagePixmap);
TQImage scaledDisplayImage = displayImage;
scaledDisplayImage = scaledDisplayImage.smoothScale(m_base->ImageInputLabel->width(), m_base->ImageInputLabel->height());
TQPixmap scaledInputImagePixmap(scaledDisplayImage);
m_base->ImageInputLabel->setPixmap(scaledInputImagePixmap);
m_inputImageViewer->setPixmap(inputImagePixmap);
}
@ -1603,7 +1623,10 @@ void FPGAViewPart::updateDisplay() {
}
}
TQPixmap outputImagePixmap(outputImage);
m_base->ImageOutputLabel->setPixmap(outputImagePixmap);
TQImage scaledOutputImage = outputImage;
scaledOutputImage = scaledOutputImage.smoothScale(m_base->ImageOutputLabel->width(), m_base->ImageOutputLabel->height());
TQPixmap scaledOutputImagePixmap(scaledOutputImage);
m_base->ImageOutputLabel->setPixmap(scaledOutputImagePixmap);
m_outputImageViewer->setPixmap(outputImagePixmap);
outputImage.save(m_dataOutputFile, "PNG");
}

5
clients/tde/src/part/fpgaview/part.h
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@ -250,7 +250,10 @@ namespace RemoteLab
TQImage m_dataInputImage;
TQFile* m_dataOutputFile;
TQByteArray m_dataByteArray;
int m_dataMemorySize;
unsigned int m_dataMemorySize;
unsigned int m_dataMemorySizePrev;
unsigned int m_dataMemoryImageWidth;
unsigned int m_dataMemoryImageHeight;
ImageViewerWindow* m_inputImageViewer;
ImageViewerWindow* m_outputImageViewer;

53
fpga/common/remote_access.v
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@ -38,7 +38,7 @@ module remote_access(
input sram_wren_in,
input sram_clock_in,
input [7:0] sram_data_in,
input [13:0] sram_address_in,
input [(RAM_ADDR_BITS-1):0] sram_address_in,
output [7:0] sram_data_out,
output sram_available,
input sram_processing_done,
@ -56,7 +56,6 @@ module remote_access(
reg [7:0] remote_access_4_bit_input_reg;
reg [7:0] remote_access_8_bit_input_reg;
reg [15:0] remote_access_16_bit_input_reg;
reg [15:0] remote_access_data_ram_size_reg = (2**RAM_ADDR_BITS);
reg [3:0] remote_access_lcd_data_out_reg;
reg remote_access_lcd_rs_out_reg;
reg remote_access_lcd_rw_out_reg;
@ -192,12 +191,12 @@ module remote_access(
reg data_storage_remote_enable = 0;
wire data_storage_clka;
wire [7:0] data_storage_dina;
wire [13:0] data_storage_addra;
wire [(RAM_ADDR_BITS-1):0] data_storage_addra;
wire data_storage_write_enable;
wire [7:0] data_storage_data_out;
reg [7:0] data_storage_dina_reg;
reg [13:0] data_storage_addra_reg;
reg [(RAM_ADDR_BITS-1):0] data_storage_addra_reg;
reg data_storage_write_enable_reg;
data_storage #(RAM_ADDR_BITS) data_storage(.clka(data_storage_clka), .dina(data_storage_dina), .addra(data_storage_addra),
@ -251,6 +250,9 @@ module remote_access(
reg transmit_main_status = 0;
reg transmit_main_status_done = 0;
reg transmit_dsp_ram_size = 0;
reg transmit_dsp_ram_size_done = 0;
reg transmit_input_status = 0;
reg transmit_input_status_done = 0;
@ -267,7 +269,7 @@ module remote_access(
reg transmit_dsp_status = 0;
reg transmit_dsp_status_done = 0;
reg transmit_dsp_status_holdoff = 0;
reg [15:0] transmit_dsp_status_counter = 0;
reg [RAM_ADDR_BITS:0] transmit_dsp_status_counter = 0;
reg transmit_led_status = 0;
reg transmit_led_status_done = 0;
@ -294,7 +296,7 @@ module remote_access(
if (tx_toggle == 0) begin
if ((transmit_4_bit_status == 1) && (transmit_4_bit_status_done == 0)) begin
TxD_data = transmitter_4_bit_state;
TxD_start = 1;
tx_toggle = 1;
@ -303,7 +305,7 @@ module remote_access(
if ((transmit_8_bit_status == 1) && (transmit_8_bit_status_done == 0)) begin
TxD_data = transmitter_8_bit_state;
TxD_start = 1;
tx_toggle = 1;
@ -330,16 +332,25 @@ module remote_access(
if ((transmit_main_status == 1) && (transmit_main_status_done == 0)) begin
TxD_data = transmitter_main_state;
TxD_start = 1;
tx_toggle = 1;
transmit_main_status_done = 1;
end
if ((transmit_dsp_ram_size == 1) && (transmit_dsp_ram_size_done == 0)) begin
TxD_data = RAM_ADDR_BITS;
TxD_start = 1;
tx_toggle = 1;
transmit_dsp_ram_size_done = 1;
end
if ((transmit_input_status == 1) && (transmit_input_status_done == 0)) begin
TxD_data = transmitter_input_state;
TxD_start = 1;
tx_toggle = 1;
@ -348,7 +359,7 @@ module remote_access(
if ((transmit_lcd_status == 1) && (transmit_lcd_status_done == 0)) begin
TxD_data = lcd_display_string[transmit_lcd_status_counter];
TxD_start = 1;
tx_toggle = 1;
@ -360,7 +371,7 @@ module remote_access(
if ((transmit_led_status == 1) && (transmit_led_status_done == 0)) begin
TxD_data = led_display_bytes[transmit_led_status_counter];
TxD_start = 1;
tx_toggle = 1;
@ -396,7 +407,7 @@ module remote_access(
if (transmit_dsp_status_counter >= (2**RAM_ADDR_BITS)) begin
transmit_dsp_status_done = 1;
data_storage_write_enable_reg = 1'bz;
data_storage_addra_reg = 14'bz;
data_storage_addra_reg = {(RAM_ADDR_BITS){1'bz}};
end
end
end
@ -424,6 +435,10 @@ module remote_access(
if (transmit_main_status == 0) begin
transmit_main_status_done = 0;
end
if (transmit_dsp_ram_size == 0) begin
transmit_dsp_ram_size_done = 0;
end
if (transmit_input_status == 0) begin
transmit_input_status_done = 0;
@ -527,6 +542,13 @@ module remote_access(
if (transmit_main_status_done == 1) begin
transmit_main_status = 0;
if (transmit_all_data_state == 1) begin
transmit_dsp_ram_size = 1;
end
end
if (transmit_dsp_ram_size_done == 1) begin
transmit_dsp_ram_size = 0;
if (transmit_all_data_state == 1) begin
transmit_4_bit_status = 1;
end
@ -599,7 +621,7 @@ module remote_access(
data_storage_remote_enable = 0;
sram_available_reg = 1;
data_storage_write_enable_reg = 1'bz;
data_storage_addra_reg = 14'bz;
data_storage_addra_reg = {(RAM_ADDR_BITS){1'bz}};
waiting_on_dsp_processing = 1;
transmit_dsp_rx_complete = 1;
next_byte_is_command_prev_command = 0;
@ -698,6 +720,11 @@ module remote_access(
// Transmit the contents of RAM...
transmit_dsp_status = 1;
end
if (serial_command_buffer == 79) begin
// Transmit the DSP RAM size
transmit_dsp_ram_size = 1;
end
end else begin
if (next_byte_is_command == 1) begin
// The previous byte was the command--now load in the data!

2
fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/data_storage.v
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@ -9,7 +9,7 @@
module data_storage(
input clka,
input [7:0] dina,
input [13:0] addra,
input [(RAM_ADDR_BITS-1):0] addra,
input wea,
output reg [7:0] douta);

20
fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.v
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@ -22,6 +22,8 @@ module main(
input serial_input,
output serial_output);
parameter RAM_ADDR_BITS = 14;
wire [7:0] four_bit_output; // Output from the user program to the remote access module
wire [7:0] four_bit_input; // Input to the user program from the remote access module
wire [7:0] eight_bit_output; // Output from the user program to the remote access module
@ -72,12 +74,12 @@ module main(
//
// Inputs:
// .clk: 50MHz clock
// .four_bit_input 4-bit input to the user program from the remote access module
// .eight_bit_input 8-bit input to the user program from the remote access module
// .four_bit_input 4-bit input to the user program from the remote access module
// .eight_bit_input 8-bit input to the user program from the remote access module
// .sixteen_bit_input 16-bit input to the user program from the remote access module
// .serial_port_receiver Input from the serial port's RxD (receive data) pin
// .remote_access_input_enable Toggle remote access input vs. local input mode
// .local_input Local input to the remote program
// .local_input Local input to the remote program
// .seize_serial_tx Sieze control of the serial transmitter from the remote control system
// .serial_tx_data Byte to be transmitted on transmit strobe if control has been siezed
// .serial_tx_strobe Transmit serial data on posedge if transmit control has been siezed
@ -87,7 +89,7 @@ module main(
// .sram_wren_in Synchronous SRAM write enable (1=write, 0=read)
// .sram_clock_in Synchronous SRAM clock input
// .sram_data_in Synchronous SRAM data input (8-bit)
// .sram_address_in Synchronous SRAM address input (14-bit)
// .sram_address_in Synchronous SRAM address input (14-bit by default)
// .sram_processing_done When 1, signal release of user control of synchronous SRAM
// .led_segment_bus Connect directly to the 8 bits controlling the LED display segments
// .led_digit_select Connect directly to the 4 bits enabling the LED display digits
@ -111,7 +113,7 @@ module main(
wire sram_wren_in;
wire sram_clock_in;
wire [7:0] sram_data_in;
wire [13:0] sram_address_in;
wire [(RAM_ADDR_BITS-1):0] sram_address_in;
wire [7:0] sram_data_out;
wire sram_available;
wire sram_processing_done;
@ -124,7 +126,7 @@ module main(
assign sram_clock_in = main_fifty_clock;
remote_access remote_access(.main_fifty_clock(main_fifty_clock), .remote_access_4_bit_output(four_bit_output),
remote_access #(RAM_ADDR_BITS) remote_access(.main_fifty_clock(main_fifty_clock), .remote_access_4_bit_output(four_bit_output),
.remote_access_4_bit_input(four_bit_input), .remote_access_8_bit_output(eight_bit_output),
.remote_access_8_bit_input(eight_bit_input), .remote_access_16_bit_output(sixteen_bit_output),
.remote_access_16_bit_input(sixteen_bit_input),
@ -286,13 +288,13 @@ module sample_image_processing_demo(clk, wren, dout, addr, din, enable, done);
output reg wren;
output reg [7:0] dout;
output reg [13:0] addr;
output reg [(RAM_ADDR_BITS-1):0] addr;
input [7:0] din;
input enable;
output reg done;
reg prev_enable;
reg [13:0] counter;
reg [(RAM_ADDR_BITS-1):0] counter;
reg toggler;
always @(posedge clk) begin
@ -310,7 +312,7 @@ module sample_image_processing_demo(clk, wren, dout, addr, din, enable, done);
wren = 1;
addr = counter;
counter = counter + 1;
if (counter >= 16383) begin
if (counter > (2**RAM_ADDR_BITS)) begin
done = 1;
end
toggler = 0;

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