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@ -105,13 +105,19 @@ module main(
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//
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//-------------------------------------------------------------------------------------------------------
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reg sram_wren_in = 0;
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wire sram_wren_in;
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wire sram_clock_in;
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reg [7:0] sram_data_in = 0;
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reg [13:0] sram_address_in = 0;
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wire [7:0] sram_data_out = 0;
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wire [7:0] sram_data_in;
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wire [13:0] sram_address_in;
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wire [7:0] sram_data_out;
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wire sram_available;
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reg sram_processing_done = 1;
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wire sram_processing_done;
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// Uncomment this block if no image processing module is provided
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// assign sram_wren_in = 0;
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// assign sram_data_in = 0;
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// assign sram_address_in = 0;
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// assign sram_processing_done = 1;
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assign sram_clock_in = main_fifty_clock;
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@ -149,6 +155,17 @@ module main(
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.sixteen_bit_output(sixteen_bit_output), .lcd_data_in_address(lcd_data_in_address),
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.lcd_data_in_data(lcd_data_in_data), .lcd_data_in_enable(lcd_data_in_enable));
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//-------------------------------------------------------------------------------------------------------
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//
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// User Image Processing Module Instantiation
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//
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// Instantiate the simple userimage processing module to invert the bits in any images sent to the FPGA
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//
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//-------------------------------------------------------------------------------------------------------
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sample_image_processing_demo sample_image_processing_demo(.clk(clk_div_by_two), .wren(sram_wren_in), .dout(sram_data_in), .addr(sram_address_in),
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.din(sram_data_out), .enable(sram_available), .done(sram_processing_done));
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endmodule
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//-------------------------------------------------------------------------------------------------------
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@ -202,3 +219,53 @@ module sample_demo(clk, four_bit_input, four_bit_output, eight_bit_input, eight_
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end
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end
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endmodule
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//-------------------------------------------------------------------------------------------------------
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//
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// Demo User Image Processing Module
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//
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//-------------------------------------------------------------------------------------------------------
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module sample_image_processing_demo(clk, wren, dout, addr, din, enable, done);
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input clk;
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output reg wren;
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output reg [7:0] dout;
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output reg [13:0] addr;
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input [7:0] din;
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input enable;
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output reg done;
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reg prev_enable;
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reg [13:0] counter;
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reg toggler;
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always @(posedge clk) begin
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if ((enable == 1) && (prev_enable == 0)) begin
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counter = 0;
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toggler = 0;
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end
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if ((enable == 1) && (done == 0)) begin
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if (toggler == 0) begin
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wren = 0;
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addr = counter;
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toggler = 1;
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end else begin
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dout = ~din;
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wren = 1;
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addr = counter;
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counter = counter + 1;
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if (counter >= 16383) begin
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done = 1;
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end
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toggler = 0;
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end
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end
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if (enable == 0) begin
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done = 0;
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addr = 0;
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toggler = 0;
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end
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prev_enable = enable;
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end
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endmodule
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