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Avoid usage of TQTimer::singleShot in the FPGA viewer part

Browse Source 
Repair "think-o" in the Spartan 6 block RAM HDL
master
Timothy Pearson 12 years ago
parent 9d5b0368df
commit 400d0abcff
3 changed files with 23 additions and 17 deletions
Show Stats Download Patch File Download Diff File

37
clients/tde/src/part/fpgaview/part.cpp
Unescape View File

@ -601,6 +601,7 @@ FPGAViewPart::FPGAViewPart(TQWidget *parentWidget, const char *widgetName, TQObj
// Create timers
m_updateTimer = new TQTimer(this);
m_timeoutTimer = new TQTimer(this);
m_connectionTimer = new TQTimer(this);
connect(m_connectionTimer, SIGNAL(timeout()), this, SLOT(finishConnectingToServer()));
@ -1054,6 +1055,7 @@ void FPGAViewPart::connectionClosed() {
void FPGAViewPart::postInit() {
setUsingFixedSize(true);
connect(m_updateTimer, SIGNAL(timeout()), this, SLOT(updateDisplay()));
connect(m_timeoutTimer, SIGNAL(timeout()), this, SLOT(updateDisplay()));
}
bool FPGAViewPart::openURL(const KURL &url) {
@ -1071,6 +1073,7 @@ bool FPGAViewPart::closeURL() {
void FPGAViewPart::disconnectFromServerCallback() {
m_updateTimer->stop();
m_timeoutTimer->stop();
}
void FPGAViewPart::connectionFinishedCallback() {
@ -1082,7 +1085,7 @@ void FPGAViewPart::connectionFinishedCallback() {
m_commHandlerMode = 0;
m_commHandlerNextState = 0;
m_commHandlerNextMode = 0;
m_updateTimer->start(FPGA_COMM_TIMEOUT_MS, TRUE);
m_timeoutTimer->start(FPGA_COMM_TIMEOUT_MS, TRUE);
processLockouts();
updateDisplay();
return;
@ -1197,16 +1200,18 @@ void FPGAViewPart::receiveInputStatesFromRemoteFPGA() {
m_tickerState = 0; \
m_commHandlerState = 0; \
m_commHandlerMode = 0; \
m_commHandlerNextState = 0; \
m_commHandlerNextMode = 0; \
m_commHandlerNextState = 0; \
m_commHandlerNextMode = 0; \
while (m_socket->bytesAvailable() > 0) { \
m_socket->readBlock(data, 64); \
} \
setStatusMessage(i18n("Debug interface timeout, still waiting for data. Please verify that the FPGA is properly configured.")); \
m_updateTimer->start(FPGA_COMM_TIMEOUT_MS, TRUE); \
m_timeoutTimer->start(FPGA_COMM_TIMEOUT_MS, TRUE); \
return;
#define POLL_FOR_DATA_IMMEDIATE TQTimer::singleShot(50, this, TQT_SLOT(updateDisplay()));
#define POLL_FOR_DATA_IMMEDIATE if (!m_updateTimer->isActive()) { \
m_updateTimer->start(50, TRUE); \
}
void FPGAViewPart::updateDisplay() {
if (m_socket) {
@ -1224,7 +1229,7 @@ void FPGAViewPart::updateDisplay() {
// Send request for all output states
m_socket->writeLine("L\r");
m_updateTimer->start(FPGA_COMM_TIMEOUT_MS, TRUE);
m_timeoutTimer->start(FPGA_COMM_TIMEOUT_MS, TRUE);
m_commHandlerState = 1;
POLL_FOR_DATA_IMMEDIATE
@ -1257,7 +1262,7 @@ void FPGAViewPart::updateDisplay() {
if (m_tickerState > 3) {
m_tickerState = 0;
}
m_updateTimer->start(FPGA_COMM_TIMEOUT_MS, TRUE);
m_timeoutTimer->start(FPGA_COMM_TIMEOUT_MS, TRUE);
m_commHandlerState = m_commHandlerNextState;
m_commHandlerMode = m_commHandlerNextMode;
@ -1273,7 +1278,7 @@ void FPGAViewPart::updateDisplay() {
}
}
else {
if (!m_updateTimer->isActive()) {
if (!m_timeoutTimer->isActive()) {
UPDATEDISPLAY_TIMEOUT
}
else {
@ -1356,7 +1361,7 @@ void FPGAViewPart::updateDisplay() {
// Send request for all output states
m_socket->writeLine("L\r");
m_updateTimer->start(FPGA_COMM_TIMEOUT_MS, TRUE);
m_timeoutTimer->start(FPGA_COMM_TIMEOUT_MS, TRUE);
m_commHandlerState = 2;
POLL_FOR_DATA_IMMEDIATE
}
@ -1383,7 +1388,7 @@ void FPGAViewPart::updateDisplay() {
m_connectionActiveAndValid = true;
setStatusMessage(i18n("Running batch test") + "...");
m_updateTimer->start(FPGA_COMM_TIMEOUT_MS, TRUE);
m_timeoutTimer->start(FPGA_COMM_TIMEOUT_MS, TRUE);
m_commHandlerState = 1;
POLL_FOR_DATA_IMMEDIATE
@ -1396,7 +1401,7 @@ void FPGAViewPart::updateDisplay() {
}
}
else {
if (!m_updateTimer->isActive()) {
if (!m_timeoutTimer->isActive()) {
m_batchOutputFile->flush();
m_batchOutputFile->close();
delete m_batchOutputFile;
@ -1416,7 +1421,7 @@ void FPGAViewPart::updateDisplay() {
int i;
if (m_commHandlerState == 0) {
m_updateTimer->stop();
m_timeoutTimer->stop();
processLockouts();
m_base->dataProcessingStatusLabel->setText(i18n("Reading input data") + "...");
m_batchInputValueList.clear();
@ -1475,7 +1480,7 @@ void FPGAViewPart::updateDisplay() {
m_base->dataProcessingProgressBar->setProgress(offset);
}
m_updateTimer->start(FPGA_DATA_PROCESSING_TIMEOUT_MS, TRUE);
m_timeoutTimer->start(FPGA_DATA_PROCESSING_TIMEOUT_MS, TRUE);
m_batchCurrentValueIndex = 0;
m_commHandlerState = 1;
@ -1512,13 +1517,13 @@ void FPGAViewPart::updateDisplay() {
m_base->dataProcessingStatusLabel->setText(i18n("Waiting for data from FPGA") + "...");
m_updateTimer->start(FPGA_DATA_PROCESSING_TIMEOUT_MS, TRUE);
m_timeoutTimer->start(FPGA_DATA_PROCESSING_TIMEOUT_MS, TRUE);
m_commHandlerState = 2;
POLL_FOR_DATA_IMMEDIATE
}
else {
if (!m_updateTimer->isActive()) {
if (!m_timeoutTimer->isActive()) {
m_dataOutputFile->flush();
m_dataOutputFile->close();
delete m_dataOutputFile;
@ -1595,7 +1600,7 @@ void FPGAViewPart::updateDisplay() {
POLL_FOR_DATA_IMMEDIATE
}
else {
if (!m_updateTimer->isActive()) {
if (!m_timeoutTimer->isActive()) {
m_dataOutputFile->flush();
m_dataOutputFile->close();
delete m_dataOutputFile;

1
clients/tde/src/part/fpgaview/part.h
Unescape View File

@ -207,6 +207,7 @@ namespace RemoteLab
FPGAViewBase* m_base;
TQMutex* m_connectionMutex;
TQTimer* m_updateTimer;
TQTimer* m_timeoutTimer;
TQPtrList<TDEAction> m_menuActionList;
TDEActionMenu* m_modeSubMenu;

2
fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/data_storage.v
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@ -14,7 +14,7 @@ module data_storage(
output reg [7:0] douta);
parameter RAM_WIDTH = 8;
parameter RAM_ADDR_BITS = 16384;
parameter RAM_ADDR_BITS = 14;
// Xilinx specific directive
(* RAM_STYLE="BLOCK" *)

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