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Move hardware design files to their correct locations

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master
Timothy Pearson 10 years ago
parent 04ab7c6632
commit a4eb2fb6bf
7 changed files with 474 additions and 510 deletions
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33
fpga/gpmc/xilinx/common/data_storage.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
// (c) 2014 Timothy Pearson, Raptor Engineering
// Released into the Public Domain
//
//////////////////////////////////////////////////////////////////////////////////
module data_storage(
input clka,
input [7:0] dina,
input [(RAM_ADDR_BITS-1):0] addra,
input wea,
output reg [7:0] douta);
parameter RAM_ADDR_BITS = 14;
parameter RAM_WIDTH = 8;
// Xilinx specific directive
(* RAM_STYLE="BLOCK" *)
reg [RAM_WIDTH-1:0] data_storage_ram [(2**RAM_ADDR_BITS)-1:0];
always @(posedge clka) begin
if (wea) begin
data_storage_ram[addra] <= dina;
douta <= dina;
end else begin
douta <= data_storage_ram[addra];
end
end
endmodule

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fpga/gpmc/xilinx/common/lcd_data_storage.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
// (c) 2014 Timothy Pearson, Raptor Engineering
// Released into the Public Domain
//
//////////////////////////////////////////////////////////////////////////////////
module lcd_data_storage(
input clka,
input clkb,
input [7:0] dina,
input [7:0] dinb,
input [4:0] addra,
input [4:0] addrb,
input wea,
input web,
output reg [7:0] douta,
output reg [7:0] doutb);
parameter RAM_WIDTH = 8;
// Xilinx specific directive
(* RAM_STYLE="BLOCK" *)
reg [RAM_WIDTH-1:0] data_storage_ram [(2**5)-1:0];
always @(posedge clka) begin
douta <= data_storage_ram[addra];
if (wea) begin
data_storage_ram[addra] <= dina;
douta <= dina;
end
end
always @(posedge clkb) begin
doutb <= data_storage_ram[addrb];
if (web) begin
data_storage_ram[addrb] <= dinb;
doutb <= dinb;
end
end
endmodule

393
fpga/gpmc/xilinx/common/main.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
// uLab to ARM GPMC interface
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//
// (c) 2014 Timothy Pearson
// Raptor Engineering
// http://www.raptorengineeringinc.com
//
//////////////////////////////////////////////////////////////////////////////////
module main(
input clk,
input gpmc_advn,
input gpmc_oen,
input gpmc_wen,
inout [7:0] gpmc_data,
input [RAM_ADDR_BITS:0] gpmc_address,
input usermem_wen,
output reg usermem_wait,
inout [7:0] usermem_data,
inout [RAM_ADDR_BITS:0] usermem_address,
output reg userproc_start,
input userproc_done,
input [3:0] four_bit_leds,
input [7:0] eight_bit_leds,
output reg [3:0] four_bit_switches,
output reg [7:0] eight_bit_switches,
inout [15:0] sixteen_bit_io,
input sixteen_bit_io_wen,
output reg sixteen_bit_io_mode,
input [3:0] sseg_mux,
input [7:0] sseg_data);
parameter RAM_ADDR_BITS = 14;
reg [15:0] sixteen_bit_io_in;
reg [15:0] sixteen_bit_io_out;
reg [15:0] sixteen_bit_io_reg;
reg sixteen_bit_io_wen_reg;
assign sixteen_bit_io = (sixteen_bit_io_wen) ? sixteen_bit_io_out : 16'bz;
always @(posedge clk) begin
sixteen_bit_io_reg = sixteen_bit_io;
sixteen_bit_io_wen_reg = sixteen_bit_io_wen;
if (sixteen_bit_io_wen_reg == 1'b0) begin
sixteen_bit_io_mode = 1'b1;
sixteen_bit_io_in = sixteen_bit_io_reg;
end else begin
sixteen_bit_io_mode = 1'b0;
end
end
reg [7:0] gpmc_data_out;
reg gpmc_data_driven;
assign gpmc_data = (gpmc_data_driven) ? gpmc_data_out : 8'bz;
reg [7:0] usermem_data_out;
assign usermem_data = (usermem_wen) ? usermem_data_out : 8'bz;
wire data_storage_clka;
reg [7:0] data_storage_dina;
reg [(RAM_ADDR_BITS-1):0] data_storage_addra;
reg data_storage_write_enable;
wire [7:0] data_storage_data_out;
assign data_storage_clka = clk;
data_storage #(RAM_ADDR_BITS) data_storage(.clka(data_storage_clka), .dina(data_storage_dina), .addra(data_storage_addra),
.wea(data_storage_write_enable), .douta(data_storage_data_out));
wire lcd_data_storage_clka;
wire lcd_data_storage_clkb;
reg [7:0] lcd_data_storage_dina;
reg [7:0] lcd_data_storage_dinb;
reg [4:0] lcd_data_storage_addra;
reg [4:0] lcd_data_storage_addrb;
reg lcd_data_storage_wea;
reg lcd_data_storage_web;
wire [7:0] lcd_data_storage_douta;
wire [7:0] lcd_data_storage_doutb;
assign lcd_data_storage_clka = clk;
assign lcd_data_storage_clkb = clk;
lcd_data_storage lcd_data_storage(.clka(lcd_data_storage_clka), .clkb(lcd_data_storage_clkb),
.dina(lcd_data_storage_dina), .dinb(lcd_data_storage_dinb),
.addra(lcd_data_storage_addra), .addrb(lcd_data_storage_addrb),
.wea(lcd_data_storage_wea), .web(lcd_data_storage_web),
.douta(lcd_data_storage_douta), .doutb(lcd_data_storage_doutb));
//-----------------------------------------------------------------------------------
//
// Create a 12.5MHz clock for the seven-segement LED emulator
//
//-----------------------------------------------------------------------------------
reg clk_div_by_two;
reg clk_div_by_two_oneeighty;
reg clk_div_by_four;
reg clk_div_by_eight;
reg clk_div_by_sixteen;
always @(posedge clk) begin
clk_div_by_two = !clk_div_by_two;
end
always @(negedge clk_div_by_two) begin
clk_div_by_two_oneeighty = !clk_div_by_two_oneeighty;
end
always @(posedge clk_div_by_two_oneeighty) begin
clk_div_by_four = !clk_div_by_four;
end
always @(posedge clk_div_by_four) begin
clk_div_by_eight = !clk_div_by_eight;
end
always @(posedge clk_div_by_eight) begin
clk_div_by_sixteen = !clk_div_by_sixteen;
end
//-----------------------------------------------------------------------------------
//
// Keep track of what is on the LED display
//
//-----------------------------------------------------------------------------------
reg [7:0] led_display_bytes [3:0];
reg [17:0] digit_blanker_1 = 0;
reg [17:0] digit_blanker_2 = 0;
reg [17:0] digit_blanker_3 = 0;
reg [17:0] digit_blanker_4 = 0;
reg [7:0] sseg_data_latch;
reg [3:0] sseg_mux_latch;
always @(negedge clk_div_by_sixteen) begin
sseg_data_latch = sseg_data;
sseg_mux_latch = sseg_mux;
if (sseg_mux_latch[0] == 0) begin
led_display_bytes[0] = sseg_data_latch;
digit_blanker_1 = 0;
digit_blanker_2 = digit_blanker_2 + 1;
digit_blanker_3 = digit_blanker_3 + 1;
digit_blanker_4 = digit_blanker_4 + 1;
end
if (sseg_mux_latch[1] == 0) begin
led_display_bytes[1] = sseg_data_latch;
digit_blanker_1 = digit_blanker_1 + 1;
digit_blanker_2 = 0;
digit_blanker_3 = digit_blanker_3 + 1;
digit_blanker_4 = digit_blanker_4 + 1;
end
if (sseg_mux_latch[2] == 0) begin
led_display_bytes[2] = sseg_data_latch;
digit_blanker_1 = digit_blanker_1 + 1;
digit_blanker_2 = digit_blanker_2 + 1;
digit_blanker_3 = 0;
digit_blanker_4 = digit_blanker_4 + 1;
end
if (sseg_mux_latch[3] == 0) begin
led_display_bytes[3] = sseg_data_latch;
digit_blanker_1 = digit_blanker_1 + 1;
digit_blanker_2 = digit_blanker_2 + 1;
digit_blanker_3 = digit_blanker_3 + 1;
digit_blanker_4 = 0;
end
if (digit_blanker_1 > 128000) begin
led_display_bytes[0] = 255;
end
if (digit_blanker_2 > 128000) begin
led_display_bytes[1] = 255;
end
if (digit_blanker_3 > 128000) begin
led_display_bytes[2] = 255;
end
if (digit_blanker_4 > 128000) begin
led_display_bytes[3] = 255;
end
end
//-----------------------------------------------------------------------------------
//
// Memory and register access
//
//-----------------------------------------------------------------------------------
reg gpmc_advn_reg;
reg gpmc_oen_reg;
reg gpmc_wen_reg;
reg [7:0] gpmc_data_reg;
reg [RAM_ADDR_BITS:0] gpmc_address_reg;
reg usermem_wen_reg;
reg [7:0] usermem_data_reg;
reg [RAM_ADDR_BITS:0] usermem_address_reg;
always @(posedge clk) begin
usermem_wen_reg = usermem_wen;
usermem_data_reg = usermem_data;
usermem_address_reg = usermem_address;
gpmc_advn_reg = gpmc_advn;
gpmc_oen_reg = gpmc_oen;
gpmc_wen_reg = gpmc_wen;
gpmc_data_reg = gpmc_data;
if (gpmc_advn_reg == 1'b0) begin
gpmc_address_reg = gpmc_address;
data_storage_write_enable = 1'b0;
lcd_data_storage_wea = 1'b0;
end
if (gpmc_address_reg[RAM_ADDR_BITS] == 1'b1) begin
// System memory access
usermem_wait = 1'b1;
if (gpmc_wen_reg == 1'b0) begin
data_storage_addra = gpmc_address_reg[(RAM_ADDR_BITS-1):0];
data_storage_dina = gpmc_data_reg;
data_storage_write_enable = 1'b1;
end else begin
data_storage_addra = gpmc_address_reg[(RAM_ADDR_BITS-1):0];
data_storage_write_enable = 1'b0;
gpmc_data_out = data_storage_data_out;
end
end else begin
// User memory access
usermem_wait = 1'b0;
if (usermem_address_reg[RAM_ADDR_BITS] == 1'b1) begin
// Interdevice communication region
// MEMORY MAP
// 0x20 - 0x3f: LCD data area
if (usermem_wen_reg == 1'b0) begin
if (usermem_address_reg[(RAM_ADDR_BITS-1):5] == 1) begin // Address range 0x20 - 0x3f
lcd_data_storage_addrb = usermem_address_reg[4:0];
lcd_data_storage_dinb = usermem_data_reg;
lcd_data_storage_web = 1'b1;
end
end else begin
if (usermem_address_reg[(RAM_ADDR_BITS-1):5] == 1) begin // Address range 0x20 - 0x3f
lcd_data_storage_addrb = usermem_address_reg[4:0];
lcd_data_storage_web = 1'b0;
usermem_data_out = lcd_data_storage_doutb;
end else begin
// Default
usermem_data_out = 8'b00000000;
end
end
end else begin
// Client scratchpad memory area
if (usermem_wen_reg == 1'b0) begin
data_storage_addra = usermem_address_reg[(RAM_ADDR_BITS-1):0];
data_storage_dina = usermem_data_reg;
data_storage_write_enable = 1'b1;
end else begin
data_storage_addra = usermem_address_reg[(RAM_ADDR_BITS-1):0];
data_storage_write_enable = 1'b0;
usermem_data_out = data_storage_data_out;
end
end
// Configuration register access
// MEMORY MAP
// 0x00: Model number (read only)
// 0x01: Version (read only)
// 0x02: 4-bit I/O (lower 4 bits only)
// 0x03: 8-bit I/O
// 0x04: 16-bit I/O (upper 8 bits)
// 0x05: 16-bit I/O (lower 8 bits)
// 0x06: 7-segment LED digit 0 (read only)
// 0x07: 7-segment LED digit 1 (read only)
// 0x08: 7-segment LED digit 2 (read only)
// 0x09: 7-segment LED digit 3 (read only)
// 0x0a: User process register
// Bit 0: User processing start
// Bit 1: User processing done (read only)
// 0x20 - 0x3f: LCD data area
if (gpmc_wen_reg == 1'b0) begin
if (gpmc_address_reg[(RAM_ADDR_BITS-1):5] == 1) begin // Address range 0x20 - 0x3f
lcd_data_storage_addra = gpmc_address_reg[4:0];
lcd_data_storage_dina = gpmc_data_reg;
lcd_data_storage_wea = 1'b1;
end else begin
case (gpmc_address_reg[(RAM_ADDR_BITS-1):0])
2: begin
four_bit_switches = gpmc_data_reg[3:0];
end
3: begin
eight_bit_switches = gpmc_data_reg;
end
4: begin
sixteen_bit_io_out[15:8] = gpmc_data_reg;
end
5: begin
sixteen_bit_io_out[7:0] = gpmc_data_reg;
end
10: begin
userproc_start = gpmc_data_reg[0];
end
default: begin
// Do nothing
end
endcase
end
end else begin
if (gpmc_address_reg[(RAM_ADDR_BITS-1):5] == 1) begin // Address range 0x20 - 0x3f
lcd_data_storage_addra = gpmc_address_reg[4:0];
lcd_data_storage_wea = 1'b0;
gpmc_data_out = lcd_data_storage_douta;
end else begin
case (gpmc_address_reg[(RAM_ADDR_BITS-1):0])
0: begin
gpmc_data_out = 8'b01000010;
end
1: begin
gpmc_data_out = 8'b00000001;
end
2: begin
gpmc_data_out[7:4] = 0;
gpmc_data_out[3:0] = four_bit_leds;
end
3: begin
gpmc_data_out = eight_bit_leds;
end
4: begin
gpmc_data_out = sixteen_bit_io_in[15:8];
end
5: begin
gpmc_data_out = sixteen_bit_io_in[7:0];
end
6: begin
gpmc_data_out = led_display_bytes[0];
end
7: begin
gpmc_data_out = led_display_bytes[1];
end
8: begin
gpmc_data_out = led_display_bytes[2];
end
9: begin
gpmc_data_out = led_display_bytes[3];
end
10: begin
gpmc_data_out[0] = userproc_start;
gpmc_data_out[1] = userproc_done;
gpmc_data_out[7:2] = 0;
end
default: begin
gpmc_data_out = 0;
end
endcase
end
end
end
gpmc_data_driven = ((~gpmc_oen) && gpmc_wen);
end
endmodule

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fpga/gpmc/xilinx/numato/spartan6/xc6slx9/data_storage.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
// (c) 2014 Timothy Pearson, Raptor Engineering
// Released into the Public Domain
//
//////////////////////////////////////////////////////////////////////////////////
module data_storage(
input clka,
input [7:0] dina,
input [(RAM_ADDR_BITS-1):0] addra,
input wea,
output reg [7:0] douta);
parameter RAM_ADDR_BITS = 14;
parameter RAM_WIDTH = 8;
// Xilinx specific directive
(* RAM_STYLE="BLOCK" *)
reg [RAM_WIDTH-1:0] data_storage_ram [(2**RAM_ADDR_BITS)-1:0];
always @(posedge clka) begin
if (wea) begin
data_storage_ram[addra] <= dina;
douta <= dina;
end else begin
douta <= data_storage_ram[addra];
end
end
endmodule

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fpga/gpmc/xilinx/numato/spartan6/xc6slx9/data_storage.v
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../../../common/data_storage.v

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fpga/gpmc/xilinx/numato/spartan6/xc6slx9/lcd_data_storage.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
// (c) 2014 Timothy Pearson, Raptor Engineering
// Released into the Public Domain
//
//////////////////////////////////////////////////////////////////////////////////
module lcd_data_storage(
input clka,
input clkb,
input [7:0] dina,
input [7:0] dinb,
input [4:0] addra,
input [4:0] addrb,
input wea,
input web,
output reg [7:0] douta,
output reg [7:0] doutb);
parameter RAM_WIDTH = 8;
// Xilinx specific directive
(* RAM_STYLE="BLOCK" *)
reg [RAM_WIDTH-1:0] data_storage_ram [(2**5)-1:0];
always @(posedge clka) begin
douta <= data_storage_ram[addra];
if (wea) begin
data_storage_ram[addra] <= dina;
douta <= dina;
end
end
always @(posedge clkb) begin
doutb <= data_storage_ram[addrb];
if (web) begin
data_storage_ram[addrb] <= dinb;
doutb <= dinb;
end
end
endmodule

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fpga/gpmc/xilinx/numato/spartan6/xc6slx9/lcd_data_storage.v
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../../../common/lcd_data_storage.v

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fpga/gpmc/xilinx/numato/spartan6/xc6slx9/main.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
// uLab to ARM GPMC interface
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//
// (c) 2014 Timothy Pearson
// Raptor Engineering
// http://www.raptorengineeringinc.com
//
//////////////////////////////////////////////////////////////////////////////////
module main(
input clk,
input gpmc_advn,
input gpmc_oen,
input gpmc_wen,
inout [7:0] gpmc_data,
input [RAM_ADDR_BITS:0] gpmc_address,
input usermem_wen,
output reg usermem_wait,
inout [7:0] usermem_data,
inout [RAM_ADDR_BITS:0] usermem_address,
output reg userproc_start,
input userproc_done,
input [3:0] four_bit_leds,
input [7:0] eight_bit_leds,
output reg [3:0] four_bit_switches,
output reg [7:0] eight_bit_switches,
inout [15:0] sixteen_bit_io,
input sixteen_bit_io_wen,
output reg sixteen_bit_io_mode,
input [3:0] sseg_mux,
input [7:0] sseg_data);
parameter RAM_ADDR_BITS = 14;
reg [15:0] sixteen_bit_io_in;
reg [15:0] sixteen_bit_io_out;
reg [15:0] sixteen_bit_io_reg;
reg sixteen_bit_io_wen_reg;
assign sixteen_bit_io = (sixteen_bit_io_wen) ? sixteen_bit_io_out : 16'bz;
always @(posedge clk) begin
sixteen_bit_io_reg = sixteen_bit_io;
sixteen_bit_io_wen_reg = sixteen_bit_io_wen;
if (sixteen_bit_io_wen_reg == 1'b0) begin
sixteen_bit_io_mode = 1'b1;
sixteen_bit_io_in = sixteen_bit_io_reg;
end else begin
sixteen_bit_io_mode = 1'b0;
end
end
reg [7:0] gpmc_data_out;
reg gpmc_data_driven;
assign gpmc_data = (gpmc_data_driven) ? gpmc_data_out : 8'bz;
reg [7:0] usermem_data_out;
assign usermem_data = (usermem_wen) ? usermem_data_out : 8'bz;
wire data_storage_clka;
reg [7:0] data_storage_dina;
reg [(RAM_ADDR_BITS-1):0] data_storage_addra;
reg data_storage_write_enable;
wire [7:0] data_storage_data_out;
assign data_storage_clka = clk;
data_storage #(RAM_ADDR_BITS) data_storage(.clka(data_storage_clka), .dina(data_storage_dina), .addra(data_storage_addra),
.wea(data_storage_write_enable), .douta(data_storage_data_out));
wire lcd_data_storage_clka;
wire lcd_data_storage_clkb;
reg [7:0] lcd_data_storage_dina;
reg [7:0] lcd_data_storage_dinb;
reg [4:0] lcd_data_storage_addra;
reg [4:0] lcd_data_storage_addrb;
reg lcd_data_storage_wea;
reg lcd_data_storage_web;
wire [7:0] lcd_data_storage_douta;
wire [7:0] lcd_data_storage_doutb;
assign lcd_data_storage_clka = clk;
assign lcd_data_storage_clkb = clk;
lcd_data_storage lcd_data_storage(.clka(lcd_data_storage_clka), .clkb(lcd_data_storage_clkb),
.dina(lcd_data_storage_dina), .dinb(lcd_data_storage_dinb),
.addra(lcd_data_storage_addra), .addrb(lcd_data_storage_addrb),
.wea(lcd_data_storage_wea), .web(lcd_data_storage_web),
.douta(lcd_data_storage_douta), .doutb(lcd_data_storage_doutb));
//-----------------------------------------------------------------------------------
//
// Create a 12.5MHz clock for the seven-segement LED emulator
//
//-----------------------------------------------------------------------------------
reg clk_div_by_two;
reg clk_div_by_two_oneeighty;
reg clk_div_by_four;
reg clk_div_by_eight;
reg clk_div_by_sixteen;
always @(posedge clk) begin
clk_div_by_two = !clk_div_by_two;
end
always @(negedge clk_div_by_two) begin
clk_div_by_two_oneeighty = !clk_div_by_two_oneeighty;
end
always @(posedge clk_div_by_two_oneeighty) begin
clk_div_by_four = !clk_div_by_four;
end
always @(posedge clk_div_by_four) begin
clk_div_by_eight = !clk_div_by_eight;
end
always @(posedge clk_div_by_eight) begin
clk_div_by_sixteen = !clk_div_by_sixteen;
end
//-----------------------------------------------------------------------------------
//
// Keep track of what is on the LED display
//
//-----------------------------------------------------------------------------------
reg [7:0] led_display_bytes [3:0];
reg [17:0] digit_blanker_1 = 0;
reg [17:0] digit_blanker_2 = 0;
reg [17:0] digit_blanker_3 = 0;
reg [17:0] digit_blanker_4 = 0;
reg [7:0] sseg_data_latch;
reg [3:0] sseg_mux_latch;
always @(negedge clk_div_by_sixteen) begin
sseg_data_latch = sseg_data;
sseg_mux_latch = sseg_mux;
if (sseg_mux_latch[0] == 0) begin
led_display_bytes[0] = sseg_data_latch;
digit_blanker_1 = 0;
digit_blanker_2 = digit_blanker_2 + 1;
digit_blanker_3 = digit_blanker_3 + 1;
digit_blanker_4 = digit_blanker_4 + 1;
end
if (sseg_mux_latch[1] == 0) begin
led_display_bytes[1] = sseg_data_latch;
digit_blanker_1 = digit_blanker_1 + 1;
digit_blanker_2 = 0;
digit_blanker_3 = digit_blanker_3 + 1;
digit_blanker_4 = digit_blanker_4 + 1;
end
if (sseg_mux_latch[2] == 0) begin
led_display_bytes[2] = sseg_data_latch;
digit_blanker_1 = digit_blanker_1 + 1;
digit_blanker_2 = digit_blanker_2 + 1;
digit_blanker_3 = 0;
digit_blanker_4 = digit_blanker_4 + 1;
end
if (sseg_mux_latch[3] == 0) begin
led_display_bytes[3] = sseg_data_latch;
digit_blanker_1 = digit_blanker_1 + 1;
digit_blanker_2 = digit_blanker_2 + 1;
digit_blanker_3 = digit_blanker_3 + 1;
digit_blanker_4 = 0;
end
if (digit_blanker_1 > 128000) begin
led_display_bytes[0] = 255;
end
if (digit_blanker_2 > 128000) begin
led_display_bytes[1] = 255;
end
if (digit_blanker_3 > 128000) begin
led_display_bytes[2] = 255;
end
if (digit_blanker_4 > 128000) begin
led_display_bytes[3] = 255;
end
end
//-----------------------------------------------------------------------------------
//
// Memory and register access
//
//-----------------------------------------------------------------------------------
reg gpmc_advn_reg;
reg gpmc_oen_reg;
reg gpmc_wen_reg;
reg [7:0] gpmc_data_reg;
reg [RAM_ADDR_BITS:0] gpmc_address_reg;
reg usermem_wen_reg;
reg [7:0] usermem_data_reg;
reg [RAM_ADDR_BITS:0] usermem_address_reg;
always @(posedge clk) begin
usermem_wen_reg = usermem_wen;
usermem_data_reg = usermem_data;
usermem_address_reg = usermem_address;
gpmc_advn_reg = gpmc_advn;
gpmc_oen_reg = gpmc_oen;
gpmc_wen_reg = gpmc_wen;
gpmc_data_reg = gpmc_data;
if (gpmc_advn_reg == 1'b0) begin
gpmc_address_reg = gpmc_address;
data_storage_write_enable = 1'b0;
lcd_data_storage_wea = 1'b0;
end
if (gpmc_address_reg[RAM_ADDR_BITS] == 1'b1) begin
// System memory access
usermem_wait = 1'b1;
if (gpmc_wen_reg == 1'b0) begin
data_storage_addra = gpmc_address_reg[(RAM_ADDR_BITS-1):0];
data_storage_dina = gpmc_data_reg;
data_storage_write_enable = 1'b1;
end else begin
data_storage_addra = gpmc_address_reg[(RAM_ADDR_BITS-1):0];
data_storage_write_enable = 1'b0;
gpmc_data_out = data_storage_data_out;
end
end else begin
// User memory access
usermem_wait = 1'b0;
if (usermem_address_reg[RAM_ADDR_BITS] == 1'b1) begin
// Interdevice communication region
// MEMORY MAP
// 0x20 - 0x3f: LCD data area
if (usermem_wen_reg == 1'b0) begin
if (usermem_address_reg[(RAM_ADDR_BITS-1):5] == 1) begin // Address range 0x20 - 0x3f
lcd_data_storage_addrb = usermem_address_reg[4:0];
lcd_data_storage_dinb = usermem_data_reg;
lcd_data_storage_web = 1'b1;
end
end else begin
if (usermem_address_reg[(RAM_ADDR_BITS-1):5] == 1) begin // Address range 0x20 - 0x3f
lcd_data_storage_addrb = usermem_address_reg[4:0];
lcd_data_storage_web = 1'b0;
usermem_data_out = lcd_data_storage_doutb;
end else begin
// Default
usermem_data_out = 8'b00000000;
end
end
end else begin
// Client scratchpad memory area
if (usermem_wen_reg == 1'b0) begin
data_storage_addra = usermem_address_reg[(RAM_ADDR_BITS-1):0];
data_storage_dina = usermem_data_reg;
data_storage_write_enable = 1'b1;
end else begin
data_storage_addra = usermem_address_reg[(RAM_ADDR_BITS-1):0];
data_storage_write_enable = 1'b0;
usermem_data_out = data_storage_data_out;
end
end
// Configuration register access
// MEMORY MAP
// 0x00: Model number (read only)
// 0x01: Version (read only)
// 0x02: 4-bit I/O (lower 4 bits only)
// 0x03: 8-bit I/O
// 0x04: 16-bit I/O (upper 8 bits)
// 0x05: 16-bit I/O (lower 8 bits)
// 0x06: 7-segment LED digit 0 (read only)
// 0x07: 7-segment LED digit 1 (read only)
// 0x08: 7-segment LED digit 2 (read only)
// 0x09: 7-segment LED digit 3 (read only)
// 0x0a: User process register
// Bit 0: User processing start
// Bit 1: User processing done (read only)
// 0x20 - 0x3f: LCD data area
if (gpmc_wen_reg == 1'b0) begin
if (gpmc_address_reg[(RAM_ADDR_BITS-1):5] == 1) begin // Address range 0x20 - 0x3f
lcd_data_storage_addra = gpmc_address_reg[4:0];
lcd_data_storage_dina = gpmc_data_reg;
lcd_data_storage_wea = 1'b1;
end else begin
case (gpmc_address_reg[(RAM_ADDR_BITS-1):0])
2: begin
four_bit_switches = gpmc_data_reg[3:0];
end
3: begin
eight_bit_switches = gpmc_data_reg;
end
4: begin
sixteen_bit_io_out[15:8] = gpmc_data_reg;
end
5: begin
sixteen_bit_io_out[7:0] = gpmc_data_reg;
end
10: begin
userproc_start = gpmc_data_reg[0];
end
default: begin
// Do nothing
end
endcase
end
end else begin
if (gpmc_address_reg[(RAM_ADDR_BITS-1):5] == 1) begin // Address range 0x20 - 0x3f
lcd_data_storage_addra = gpmc_address_reg[4:0];
lcd_data_storage_wea = 1'b0;
gpmc_data_out = lcd_data_storage_douta;
end else begin
case (gpmc_address_reg[(RAM_ADDR_BITS-1):0])
0: begin
gpmc_data_out = 8'b01000010;
end
1: begin
gpmc_data_out = 8'b00000001;
end
2: begin
gpmc_data_out[7:4] = 0;
gpmc_data_out[3:0] = four_bit_leds;
end
3: begin
gpmc_data_out = eight_bit_leds;
end
4: begin
gpmc_data_out = sixteen_bit_io_in[15:8];
end
5: begin
gpmc_data_out = sixteen_bit_io_in[7:0];
end
6: begin
gpmc_data_out = led_display_bytes[0];
end
7: begin
gpmc_data_out = led_display_bytes[1];
end
8: begin
gpmc_data_out = led_display_bytes[2];
end
9: begin
gpmc_data_out = led_display_bytes[3];
end
10: begin
gpmc_data_out[0] = userproc_start;
gpmc_data_out[1] = userproc_done;
gpmc_data_out[7:2] = 0;
end
default: begin
gpmc_data_out = 0;
end
endcase
end
end
end
gpmc_data_driven = ((~gpmc_oen) && gpmc_wen);
end
endmodule

1
fpga/gpmc/xilinx/numato/spartan6/xc6slx9/main.v
Unescape View File

@ -0,0 +1 @@
../../../common/main.v

41
fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ulab_debug_interface.xise
Unescape View File

@ -34,9 +34,7 @@
<properties>
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
@ -50,8 +48,6 @@
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
@ -68,55 +64,44 @@
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
@ -124,12 +109,10 @@
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
@ -156,12 +139,9 @@
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
@ -179,7 +159,6 @@
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
@ -200,7 +179,6 @@
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
@ -212,7 +190,6 @@
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
@ -244,7 +221,6 @@
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
@ -252,9 +228,7 @@
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="main_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="main_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="main_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
@ -272,7 +246,6 @@
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
@ -297,7 +270,6 @@
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
@ -305,12 +277,10 @@
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
@ -325,8 +295,6 @@
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
@ -351,27 +319,20 @@
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>

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