23 Commits (abb005c39c7e053dd40e4577430bfff56b03859e)

Author SHA1 Message Date
Timothy Pearson 0ffb793cb5 Relayout the GUI to be more in line with expected norms
11 years ago
Timothy Pearson 04ab7c6632 Add initial GOMC compatible uLab debug system hardware design files
11 years ago
Timothy Pearson 963b88fb0b Add initial GPMC test program and associated files for BeagleBone Black
11 years ago
Timothy Pearson 38c56c7c1f Add initial version of SVF player for Beaglebone Black
11 years ago
Timothy Pearson 26c1236cdc Fix prior commit
11 years ago
Timothy Pearson 5c2d024b38 Fix progress bar not moving during DSP data reception
11 years ago
Timothy Pearson f27e0f0184 Allow data processing RAM size to be configured by changing a Verilog parameter on the FPGA side
11 years ago
Timothy Pearson 8faa3da109 Fix image distortion when certain greyscale values are utilized
11 years ago
Timothy Pearson 7997af3f4f Fix 7-segment LED display and add sample driver for the same
11 years ago
Timothy Pearson 976f4c5dfe Use 10-pin headers for ulab debug interface serial port on Spartan 6
12 years ago
Timothy Pearson 3f00d517b8 Add sample image processing module to Spartan 6 demo project
12 years ago
Timothy Pearson 401379667e Properly report device programming errors
12 years ago
Timothy Pearson 400d0abcff Avoid usage of TQTimer::singleShot in the FPGA viewer part
12 years ago
Timothy Pearson 9d5b0368df Add sample design for Spartan 6 and ISE 14.4
12 years ago
Timothy Pearson 40acabc2bf Update remote debug module and clean up FPGA section of the source tree
12 years ago
Timothy Pearson 1e0e205356 Add verified Xilinx programming script and device type extractor
12 years ago
Timothy Pearson f1ead12600 Minor cleanup
12 years ago
Timothy Pearson f0c477eef4 Add magic 64 bytes to S6 svf file
12 years ago
Timothy Pearson d94bf35fe7 Add initial untested support for Spartan 6 devices
12 years ago
Timothy Pearson 9c6d284d49 Initial rpi jtag support
12 years ago
Timothy Pearson 7643298424 Update makefiles
12 years ago
Timothy Pearson d1b70f8018 Add initial files for direct FPGA programming
12 years ago
Timothy Pearson db7e77be8f Add public domain FPGA files for Xilinx s3/s3e
13 years ago