abb005c39c
Update more copyright dates
6 years ago
28bb9c7919
Fix FTBFS from TQT conversion commit
6 years ago
46155f46b1
Update copyright dates
6 years ago
480f92da42
Finish QT-->TQT conversion
6 years ago
5f9aca6f18
Add Kerberos flags to Automake include lists
6 years ago
0bdff5e886
Find Heimdal kerberos in multidev packages on Debian and Ubuntu
6 years ago
e363f97f5b
Reset submodule clients/tde/cmake to latest HEAD
6 years ago
6990a27c1d
Reset submodule clients/tde/admin to latest HEAD
6 years ago
a08c8fe35d
Fix math traces failing after normal scope updates randomly set current destination trace
7 years ago
964f9570c0
Fix crash on reconnect
8 years ago
85ec50c70f
Switch package format to quilt on Debian and Ubuntu
8 years ago
c9c5184d21
Allow reconnection after certain types of disconnection event
8 years ago
063c820d6a
Fix crash on sensor monitor startup
8 years ago
d8856bdf08
Fix FTBFS on Debian
8 years ago
960feb147a
Update submodules to latest HEAD
8 years ago
e4fcc7fd8f
Restore measured parameters when waveform file is loaded
...
Consolidate parameter set routines
9 years ago
c62b282dff
Save sweep parameters in waveform file
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Minor update to control lockout rules
9 years ago
5d4ae8c1ec
Add inital component analyzer part
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Fix a couple of Kerberos socket class threading problems
Stop drawing garbage in trace viewer when trace data partially intialized
Add FloatSpinBox explicit data accessor
9 years ago
71f607c43a
Fix minor error in FPGAViewPart sources
9 years ago
fb77cfbd28
Add seven segment display array widget
9 years ago
83cee4e365
Move seven segment display widget to common widget directory
9 years ago
f6cc7c2a0a
Update ProtoTerminal part to use threading and message queues
9 years ago
3b2621f9fe
Fix a number of memory initialization glitches
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Fix math waveform offset saving
Fix insane memory usage during SASL negotiation
10 years ago
eec55e5277
Add autodetection of FFTS library presence
10 years ago
98fc8fbcb3
Add math waveform support to scope viewer
10 years ago
c223a6a35f
Minor update to trace widget
10 years ago
b25a8045b8
Clean up autogenerated files from GIT tree
10 years ago
bd0400a096
Fix scope part crashes
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Add server-provided caption support
Properly brand client application
11 years ago
9c98267db3
Add missing Debian install file
11 years ago
5bb4cd0a02
Add trigger channel set to scope part
11 years ago
15a8d153cc
Remove accidentally included Makefile.in
11 years ago
55e9906b78
Add timebase controls to scope part
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Build debug symbols package
11 years ago
de23e8f184
Fix a number of out of range warnings
11 years ago
63b68e2dfb
Add ability to set digital trace viewer cursors with the mouse
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Fix oversized cursor control buttons
11 years ago
f65487c882
Add ability to display values of traces at selected cursor position
11 years ago
d7b08ca2de
Fill area under logical 1s in TraceWidget digital mode
11 years ago
bc7497f24c
Fix slow TraceWidget redraw
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Add proper horizontal scrolling to TraceWidget
11 years ago
98182bf21a
Update license headers in TDE client
11 years ago
1fbfe13066
First pass of logic analyzer functionality (client and FPGA core)
11 years ago
6ae28a47f7
Add left trace sidebar option to trace viewer widget
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Add scrollbar option to trace viewer widget
11 years ago
72e80dda8e
Add ability to hard reset user device
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Fix initial size of serial and terminal windows
11 years ago
2cea70caec
Automatically prompt for username/password if Kerberos ticket is invalid
11 years ago
55f109d365
Add serial console client
11 years ago
06f302400e
Fix prototerminal reception of multiple lines of text
11 years ago
1825d32921
Add prototyping terminal to uLab client for TDE
11 years ago
0ffb793cb5
Relayout the GUI to be more in line with expected norms
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Add user logic reset signal
Stabilize data transfer
11 years ago
37420cfb78
Increase DSP memory size
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Fix potential crash in FPGA viewer if hardware debug interface is malfunctioning or offline
11 years ago
4123289a7a
Update common modules
11 years ago
5c2d024b38
Fix progress bar not moving during DSP data reception
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Fix syntax error in demo main.v file
11 years ago
f27e0f0184
Allow data processing RAM size to be configured by changing a Verilog parameter on the FPGA side
11 years ago
Timothy Pearson