Timothy Pearson
|
46155f46b1
|
Update copyright dates
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6 years ago |
|
Timothy Pearson
|
1fbfe13066
|
First pass of logic analyzer functionality (client and FPGA core)
|
11 years ago |
|
Timothy Pearson
|
72e80dda8e
|
Add ability to hard reset user device
Fix initial size of serial and terminal windows
|
11 years ago |
|
Timothy Pearson
|
038275fcc0
|
Add serial I/O to host FPGA
|
11 years ago |
|
Timothy Pearson
|
061289c613
|
Max out logic analyzer memory
|
11 years ago |
|
Timothy Pearson
|
1eb48edeba
|
Add logic analyzer block to control FPGA
|
11 years ago |
|
Timothy Pearson
|
0ffb793cb5
|
Relayout the GUI to be more in line with expected norms
Add user logic reset signal
Stabilize data transfer
|
11 years ago |
|
Timothy Pearson
|
37420cfb78
|
Increase DSP memory size
Fix potential crash in FPGA viewer if hardware debug interface is malfunctioning or offline
|
11 years ago |
|
Timothy Pearson
|
a4eb2fb6bf
|
Move hardware design files to their correct locations
|
11 years ago |
|
Timothy Pearson
|
04ab7c6632
|
Add initial GOMC compatible uLab debug system hardware design files
|
11 years ago |
