8 Commits (46155f46b1fcc0063d74ae46c86ded7aeefae115)

Author SHA1 Message Date
Timothy Pearson 46155f46b1 Update copyright dates
5 years ago
Timothy Pearson 1fbfe13066 First pass of logic analyzer functionality (client and FPGA core)
10 years ago
Timothy Pearson 72e80dda8e Add ability to hard reset user device
10 years ago
Timothy Pearson 038275fcc0 Add serial I/O to host FPGA
10 years ago
Timothy Pearson 061289c613 Max out logic analyzer memory
10 years ago
Timothy Pearson 0ffb793cb5 Relayout the GUI to be more in line with expected norms
10 years ago
Timothy Pearson 37420cfb78 Increase DSP memory size
10 years ago
Timothy Pearson 04ab7c6632 Add initial GOMC compatible uLab debug system hardware design files
10 years ago