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85 lines
3.5 KiB
85 lines
3.5 KiB
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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//
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// (c) 2014 Timothy Pearson, Raptor Engineering
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// Released into the Public Domain
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//
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//////////////////////////////////////////////////////////////////////////////////
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module logic_analyzer_clock_generator(
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input clkin,
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output clkout,
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output online);
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parameter LOGIC_ANALYZER_CLOCK_MULT = 2;
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parameter LOGIC_ANALYZER_CLOCK_DIV = 2;
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wire clk0;
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wire clk2x;
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wire clkfx;
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reg reset = 1'b0;
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wire locked;
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wire [7:0] status;
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assign clkout = clkfx;
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// Only signal online if the DCM is locked and clkfx is toggling
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assign online = locked & (~status[2]);
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// DCM_SP: Digital Clock Manager
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// Spartan-6
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// Xilinx HDL Language Template, version 14.7
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DCM_SP #(
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.CLKDV_DIVIDE(2.0), // CLKDV divide value
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// (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16).
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.CLKFX_DIVIDE(LOGIC_ANALYZER_CLOCK_DIV), // Divide value on CLKFX outputs - D - (1-32)
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.CLKFX_MULTIPLY(LOGIC_ANALYZER_CLOCK_MULT), // Multiply value on CLKFX outputs - M - (2-32)
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.CLKIN_DIVIDE_BY_2("FALSE"), // CLKIN divide by two (TRUE/FALSE)
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.CLKIN_PERIOD(10.0), // Input clock period specified in nS
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.CLKOUT_PHASE_SHIFT("NONE"), // Output phase shift (NONE, FIXED, VARIABLE)
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.CLK_FEEDBACK("1X"), // Feedback source (NONE, 1X, 2X)
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.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS
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.DFS_FREQUENCY_MODE("LOW"), // Unsupported - Do not change value
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.DLL_FREQUENCY_MODE("LOW"), // Unsupported - Do not change value
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.DSS_MODE("NONE"), // Unsupported - Do not change value
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.DUTY_CYCLE_CORRECTION("TRUE"), // Unsupported - Do not change value
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.FACTORY_JF(16'hc080), // Unsupported - Do not change value
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.PHASE_SHIFT(0), // Amount of fixed phase shift (-255 to 255)
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.STARTUP_WAIT("FALSE") // Delay config DONE until DCM_SP LOCKED (TRUE/FALSE)
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)
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DCM_SP_inst (
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.CLK0(clk0), // 1-bit output: 0 degree clock output
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.CLK180(), // 1-bit output: 180 degree clock output
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.CLK270(), // 1-bit output: 270 degree clock output
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.CLK2X(clk2x), // 1-bit output: 2X clock frequency clock output
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.CLK2X180(), // 1-bit output: 2X clock frequency, 180 degree clock output
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.CLK90(), // 1-bit output: 90 degree clock output
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.CLKDV(), // 1-bit output: Divided clock output
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.CLKFX(clkfx), // 1-bit output: Digital Frequency Synthesizer output (DFS)
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.CLKFX180(), // 1-bit output: 180 degree CLKFX output
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.LOCKED(locked), // 1-bit output: DCM_SP Lock Output
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.PSDONE(), // 1-bit output: Phase shift done output
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.STATUS(status), // 8-bit output: DCM_SP status output
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.CLKFB(clk0), // 1-bit input: Clock feedback input
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.CLKIN(clkin), // 1-bit input: Clock input
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.DSSEN(1'b0), // 1-bit input: Unsupported, specify to GND.
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.PSCLK(), // 1-bit input: Phase shift clock input
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.PSEN(1'b0), // 1-bit input: Phase shift enable
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.PSINCDEC(), // 1-bit input: Phase shift increment/decrement input
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.RST(reset) // 1-bit input: Active high reset input
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);
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// End of DCM_SP_inst instantiation
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reg [7:0] reset_counter = 8'b00000001;
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always @(posedge clkin) begin
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if (reset_counter[7] == 1'b0) begin
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reset_counter = reset_counter << 1;
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reset = 1'b1;
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end else begin
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reset = 1'b0;
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end
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end
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endmodule
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