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43 lines
974 B
43 lines
974 B
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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//
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// (c) 2014 Timothy Pearson, Raptor Engineering
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// Released into the Public Domain
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//
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//////////////////////////////////////////////////////////////////////////////////
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module data_storage(
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input clka,
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input [(RAM_WIDTH-1):0] dina,
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input [(RAM_ADDR_BITS-1):0] addra,
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input wea,
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output reg [(RAM_WIDTH-1):0] douta);
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parameter RAM_ADDR_BITS = 14;
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parameter RAM_WIDTH = 8;
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// Xilinx specific directive
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(* RAM_STYLE="BLOCK" *)
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reg [RAM_WIDTH-1:0] data_storage_ram [(2**RAM_ADDR_BITS)-1:0];
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// Registered
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always @(posedge clka) begin
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if (wea) begin
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data_storage_ram[addra] <= dina;
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douta <= dina;
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end else begin
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douta <= data_storage_ram[addra];
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end
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end
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// // Unregistered
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// always @(posedge clka) begin
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// if (wea) begin
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// data_storage_ram[addra] <= dina;
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// end
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// end
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// assign douta = data_storage_ram[addra];
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endmodule
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