6 Commits (38c56c7c1fe4ecd7e5907cc14c100e4af3a87e20)

Author	SHA1	Message	Date
Timothy Pearson	8ce60c7f52	Fix prior commit	11 years ago
Timothy Pearson	f27e0f0184	Allow data processing RAM size to be configured by changing a Verilog parameter on the FPGA side	11 years ago
Timothy Pearson	8faa3da109	Fix image distortion when certain greyscale values are utilized ... Store last used values in FPGA viewer and programmer GUI for convenience on GUI restart	11 years ago
Timothy Pearson	ff484b9d9c	Fix 7 segment display malfunction at low multiplexing rates	11 years ago
Timothy Pearson	7997af3f4f	Fix 7-segment LED display and add sample driver for the same	11 years ago
Timothy Pearson	40acabc2bf	Update remote debug module and clean up FPGA section of the source tree	12 years ago