Slow demo file 7-segment clock to a more reasonable KHz value

fpga/serial/lattice/eb85/ice40_remotefpga_test/main.v

@@ -56,11 +56,11 @@ module guest_fpga_top(clk, reset, four_bit_input, four_bit_output, eight_bit_inp
 
 	// 7-segment LED display driver clock generator
 	reg sseg_clock;
-	reg [4:0] sseg_clock_counter;
+	reg [10:0] sseg_clock_counter;
 
 	always @(posedge clk) begin
 		sseg_clock_counter = sseg_clock_counter + 1;
-		if (sseg_clock_counter > 16) begin
+		if (sseg_clock_counter > 1023) begin
 			sseg_clock_counter = 0;
 			sseg_clock = ~sseg_clock;
 		end