Fix progress bar not moving during DSP data reception

Fix syntax error in demo main.v file
master
Timothy Pearson 11 years ago
parent 8ce60c7f52
commit 5c2d024b38

@ -1251,7 +1251,7 @@ void FPGAViewPart::receiveInputStatesFromRemoteFPGA() {
return; return;
#define POLL_FOR_DATA_IMMEDIATE if (!m_updateTimer->isActive()) { \ #define POLL_FOR_DATA_IMMEDIATE if (!m_updateTimer->isActive()) { \
m_updateTimer->start(50, TRUE); \ m_updateTimer->start(10, TRUE); \
} }
void FPGAViewPart::updateDisplay() { void FPGAViewPart::updateDisplay() {
@ -1598,7 +1598,6 @@ void FPGAViewPart::updateDisplay() {
while (offset < m_dataMemorySize) { while (offset < m_dataMemorySize) {
m_socket->readBlock(recData.data()+offset, 1024); m_socket->readBlock(recData.data()+offset, 1024);
offset = offset + 1024; offset = offset + 1024;
m_base->dataProcessingProgressBar->setProgress((m_dataMemorySize*2) + offset);
} }
m_base->dataProcessingStatusLabel->setText(i18n("Writing data to file") + "..."); m_base->dataProcessingStatusLabel->setText(i18n("Writing data to file") + "...");
@ -1657,6 +1656,12 @@ void FPGAViewPart::updateDisplay() {
POLL_FOR_DATA_IMMEDIATE POLL_FOR_DATA_IMMEDIATE
} }
else { else {
// Update the GUI with status information
m_base->dataProcessingProgressBar->setProgress(m_dataMemorySize + m_socket->bytesAvailable());
if (m_socket->bytesAvailable() > 0) {
m_base->dataProcessingStatusLabel->setText(i18n("Receiving data from FPGA") + "...");
}
if (!m_timeoutTimer->isActive()) { if (!m_timeoutTimer->isActive()) {
m_dataOutputFile->flush(); m_dataOutputFile->flush();
m_dataOutputFile->close(); m_dataOutputFile->close();

@ -284,17 +284,19 @@ endmodule
//------------------------------------------------------------------------------------------------------- //-------------------------------------------------------------------------------------------------------
module sample_image_processing_demo(clk, wren, dout, addr, din, enable, done); module sample_image_processing_demo(clk, wren, dout, addr, din, enable, done);
parameter IMAGE_RAM_ADDR_BITS = 14;
input clk; input clk;
output reg wren; output reg wren;
output reg [7:0] dout; output reg [7:0] dout;
output reg [(RAM_ADDR_BITS-1):0] addr; output reg [(IMAGE_RAM_ADDR_BITS-1):0] addr;
input [7:0] din; input [7:0] din;
input enable; input enable;
output reg done; output reg done;
reg prev_enable; reg prev_enable;
reg [(RAM_ADDR_BITS-1):0] counter; reg [(IMAGE_RAM_ADDR_BITS-1):0] counter;
reg toggler; reg toggler;
always @(posedge clk) begin always @(posedge clk) begin
@ -312,7 +314,7 @@ module sample_image_processing_demo(clk, wren, dout, addr, din, enable, done);
wren = 1; wren = 1;
addr = counter; addr = counter;
counter = counter + 1; counter = counter + 1;
if (counter > (2**RAM_ADDR_BITS)) begin if (counter > (2**IMAGE_RAM_ADDR_BITS)) begin
done = 1; done = 1;
end end
toggler = 0; toggler = 0;

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