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271 lines
12 KiB
271 lines
12 KiB
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: Raptor Engineering
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// Engineer: Timothy Pearson
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//
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// Design Name: Remote Access Sample Design
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// Module Name: sample_demo
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// Project Name: Remote Access Sample Design
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// Target Devices: Any
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// Description: Remote Access Sample Design
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//
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// Dependencies:
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//
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// (c) 2007-2013 Timothy Pearson, Raptor Engineering
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// Released into the Public Domain
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//
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//////////////////////////////////////////////////////////////////////////////////
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module main(
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input clk, // 100MHz clock
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// Serial port
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input serial_input,
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output serial_output);
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wire [7:0] four_bit_output; // Output from the user program to the remote access module
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wire [7:0] four_bit_input; // Input to the user program from the remote access module
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wire [7:0] eight_bit_output; // Output from the user program to the remote access module
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wire [7:0] eight_bit_input; // Input to the user program from the remote access module
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wire [15:0] sixteen_bit_output; // Output from the user program to the remote access module
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wire [15:0] sixteen_bit_input; // Input to the user program from the remote access module
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wire [7:0] remote_access_local_input;
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reg [7:0] serial_data_to_write;
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wire sieze_serial_tx;
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reg serial_tx_strobe = 0;
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wire serial_data_received;
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wire serial_rx_strobe;
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wire [5:0] lcd_data_in_address;
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wire [7:0] lcd_data_in_data;
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wire lcd_data_in_enable;
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//-------------------------------------------------------------------------------------------------------
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//
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// Generate a 50MHz clock for the remote access module
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//
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//-------------------------------------------------------------------------------------------------------
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reg main_fifty_clock = 0;
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always @(posedge clk) begin
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main_fifty_clock = !main_fifty_clock;
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end
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//-------------------------------------------------------------------------------------------------------
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//
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// Generate a 25MHz clock for the user progam
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//
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//-------------------------------------------------------------------------------------------------------
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reg clk_div_by_two = 0;
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always @(posedge main_fifty_clock) begin
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clk_div_by_two = !clk_div_by_two;
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end
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//-------------------------------------------------------------------------------------------------------
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//
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// Remote Access Module
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//
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// Inputs:
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// .clk: 50MHz clock
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// .4_bit_input 4-bit input to the user program from the remote access module
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// .8_bit_input 8-bit input to the user program from the remote access module
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// .16_bit_input 16-bit input to the user program from the remote access module
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// .serial_port_receiver Input from the serial port's RxD (receive data) pin
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// .remote_access_input_enable Toggle remote access input vs. local input mode
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// .local_input Local input to the remote program
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// .seize_serial_tx Sieze control of the serial transmitter from the remote control system
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// .serial_tx_data Byte to be transmitted on transmit strobe if control has been siezed
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// .serial_tx_strobe Transmit serial data on posedge if transmit control has been siezed
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// .lcd_data_in_address LCD character address (0-32) to write character code to
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// .lcd_data_in_data LCD character code to write to the address specified
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// .lcd_data_in_enable Enable LCD data write
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// .sram_wren_in Synchronous SRAM write enable (1=write, 0=read)
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// .sram_clock_in Synchronous SRAM clock input
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// .sram_data_in Synchronous SRAM data input (8-bit)
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// .sram_address_in Synchronous SRAM address input (14-bit)
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// .sram_processing_done When 1, signal release of user control of synchronous SRAM
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// .led_segment_bus Connect directly to the 8 bits controlling the LED display segments
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// .led_digit_select Connect directly to the 4 bits enabling the LED display digits
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//
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// Outputs:
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// .4_bit_output 4-bit output from the user program to the remote access module
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// .8_bit_output 8-bit output from the user program to the remote access module
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// .16_bit_output 16-bit output from the user program to the remote access module
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// .lcd_data_out Data output to the LCD
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// .lcd_rs_out RS signal output to the LCD
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// .lcd_rw_out RW signal output to the LCD
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// .lcd_enable_out ENABLE signal output to the LCD
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// .serial_port_transmitter Output to the serial port's TxD (transmit data) pin
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// .serial_rx_data The last received serial data
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// .serial_rx_strobe Recevied serial data valid while this signal is 1
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// .sram_data_out Synchronous SRAM data output (8-bit)
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// .sram_available Synchronous SRAM under user control
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//
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//-------------------------------------------------------------------------------------------------------
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wire sram_wren_in;
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wire sram_clock_in;
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wire [7:0] sram_data_in;
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wire [13:0] sram_address_in;
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wire [7:0] sram_data_out;
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wire sram_available;
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wire sram_processing_done;
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// Uncomment this block if no image processing module is provided
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// assign sram_wren_in = 0;
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// assign sram_data_in = 0;
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// assign sram_address_in = 0;
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// assign sram_processing_done = 1;
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assign sram_clock_in = main_fifty_clock;
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remote_access remote_access(.main_fifty_clock(main_fifty_clock), .remote_access_4_bit_output(four_bit_output),
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.remote_access_4_bit_input(four_bit_input), .remote_access_8_bit_output(eight_bit_output),
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.remote_access_8_bit_input(eight_bit_input), .remote_access_16_bit_output(sixteen_bit_output),
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.remote_access_16_bit_input(sixteen_bit_input),
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.serial_port_receiver(serial_input), .serial_port_transmitter(serial_output), .remote_access_input_enable(btn_center),
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.local_input(remote_access_local_input), .seize_serial_tx(sieze_serial_tx), .serial_tx_data(serial_data_to_write),
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.serial_tx_strobe(serial_tx_strobe), .serial_rx_data(serial_data_received), .serial_rx_strobe(serial_rx_strobe),
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.lcd_data_in_address(lcd_data_in_address), .lcd_data_in_data(lcd_data_in_data), .lcd_data_in_enable(lcd_data_in_enable),
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.sram_wren_in(sram_wren_in), .sram_clock_in(sram_clock_in), .sram_data_in(sram_data_in), .sram_address_in(sram_address_in),
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.sram_data_out(sram_data_out), .sram_available(sram_available), .sram_processing_done(sram_processing_done),
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.led_segment_bus(255), .led_digit_select(15));
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assign remote_access_local_input[7:4] = 0; // Local inputs
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assign remote_access_local_input[3:0] = 0; // Local inputs
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assign led_bank = eight_bit_input; // Mirror input to the LEDs
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assign sieze_serial_tx = 0; // Allow the remote control module to use the serial port
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// If the user module must access the serial port directly, delete
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// this assign statement and control this wire with your module.
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//-------------------------------------------------------------------------------------------------------
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//
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// User Module Instantiation
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//
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// Instantiate the simple user module to display remote access input values on the LEDs and to feed
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// button presses to the remote access module. The 16-bit remote access lines are in loopback.
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// Feel free to delete this instantiation and the module below to replace it with your module.
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//
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//-------------------------------------------------------------------------------------------------------
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sample_demo sample_demo(.clk(clk_div_by_two), .four_bit_input(four_bit_input), .four_bit_output(four_bit_output),
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.eight_bit_input(eight_bit_input), .eight_bit_output(eight_bit_output), .sixteen_bit_input(sixteen_bit_input),
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.sixteen_bit_output(sixteen_bit_output), .lcd_data_in_address(lcd_data_in_address),
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.lcd_data_in_data(lcd_data_in_data), .lcd_data_in_enable(lcd_data_in_enable));
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//-------------------------------------------------------------------------------------------------------
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//
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// User Image Processing Module Instantiation
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//
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// Instantiate the simple userimage processing module to invert the bits in any images sent to the FPGA
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//
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//-------------------------------------------------------------------------------------------------------
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sample_image_processing_demo sample_image_processing_demo(.clk(clk_div_by_two), .wren(sram_wren_in), .dout(sram_data_in), .addr(sram_address_in),
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.din(sram_data_out), .enable(sram_available), .done(sram_processing_done));
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endmodule
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//-------------------------------------------------------------------------------------------------------
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//
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// Demo User Module
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//
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//-------------------------------------------------------------------------------------------------------
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module sample_demo(clk, four_bit_input, four_bit_output, eight_bit_input, eight_bit_output, sixteen_bit_input, sixteen_bit_output, lcd_data_in_address, lcd_data_in_data, lcd_data_in_enable);
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input clk;
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input [3:0] four_bit_input;
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output reg [3:0] four_bit_output;
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input [7:0] eight_bit_input;
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output reg [7:0] eight_bit_output;
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input [15:0] sixteen_bit_input;
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output reg [15:0] sixteen_bit_output;
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output reg [5:0] lcd_data_in_address;
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output reg [7:0] lcd_data_in_data;
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output reg lcd_data_in_enable;
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reg [7:0] lcd_sample_counter = 48; // Create a sample LCD display counter register
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reg [31:0] lcd_character_change_timer = 0; // Wait a certain number of cycles before loading a new character
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reg [5:0] lcd_current_character = 0; // The current character's address
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always @(posedge clk) begin
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four_bit_output = four_bit_input; // Loopback
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eight_bit_output = eight_bit_input[3:0] + eight_bit_input[7:4]; // Sample adder
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sixteen_bit_output = sixteen_bit_input[15:8] * sixteen_bit_input[7:0]; // Sample multiplier
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// Sample LCD display routine
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lcd_data_in_address = lcd_current_character; // Character location on the LCD display
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lcd_data_in_data = lcd_sample_counter; // Character code to display
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lcd_data_in_enable = 1; // Enable data transmission
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// Cycle through all character positions
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lcd_current_character = lcd_current_character + 1;
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if (lcd_current_character > 31) begin
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lcd_current_character = 16;
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end
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// Cycle through the numbers 0 to 9 at one second intervals
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lcd_character_change_timer = lcd_character_change_timer + 1;
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if (lcd_character_change_timer > 25000000) begin // Wait one second in between character changes
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lcd_character_change_timer = 0;
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lcd_sample_counter = lcd_sample_counter + 1;
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if (lcd_sample_counter > 57) begin // Character code for the digit 9
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lcd_sample_counter = 48; // Character code for the digit 0
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end
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end
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end
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endmodule
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//-------------------------------------------------------------------------------------------------------
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//
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// Demo User Image Processing Module
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//
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//-------------------------------------------------------------------------------------------------------
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module sample_image_processing_demo(clk, wren, dout, addr, din, enable, done);
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input clk;
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output reg wren;
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output reg [7:0] dout;
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output reg [13:0] addr;
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input [7:0] din;
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input enable;
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output reg done;
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reg prev_enable;
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reg [13:0] counter;
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reg toggler;
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always @(posedge clk) begin
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if ((enable == 1) && (prev_enable == 0)) begin
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counter = 0;
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toggler = 0;
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end
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if ((enable == 1) && (done == 0)) begin
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if (toggler == 0) begin
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wren = 0;
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addr = counter;
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toggler = 1;
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end else begin
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dout = ~din;
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wren = 1;
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addr = counter;
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counter = counter + 1;
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if (counter >= 16383) begin
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done = 1;
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end
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toggler = 0;
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end
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end
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if (enable == 0) begin
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done = 0;
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addr = 0;
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toggler = 0;
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end
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prev_enable = enable;
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end
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endmodule |