Add serial I/O to host FPGA

master
Timothy Pearson 11 years ago
parent dc91899c25
commit 038275fcc0

@ -42,6 +42,11 @@ module main(
output reg userlogic_reset,
input userlogic_clock,
output userlogic_serial_txd,
input userlogic_serial_rxd,
output host_serial_txd,
input host_serial_rxd,
input [3:0] four_bit_leds,
input [7:0] eight_bit_leds,
@ -57,6 +62,9 @@ module main(
parameter RAM_ADDR_BITS = 15;
assign host_serial_txd = userlogic_serial_rxd;
assign userlogic_serial_txd = host_serial_rxd;
reg [15:0] sixteen_bit_io_in;
reg [15:0] sixteen_bit_io_out;
reg [15:0] sixteen_bit_io_reg;

@ -43,6 +43,11 @@ NET "userproc_done" LOC = "L13" | IOSTANDARD = "LVCMOS33";
NET "userlogic_reset" LOC = "E13" | SLEW = FAST | IOSTANDARD = "LVCMOS33";
NET "userlogic_clock" LOC = "F13" | IOSTANDARD = "LVCMOS33";
NET "userlogic_serial_txd" LOC = "C14" | SLEW = FAST | IOSTANDARD = "LVCMOS33";
NET "userlogic_serial_rxd" LOC = "D14" | IOSTANDARD = "LVCMOS33";
NET "host_serial_txd" LOC = "B16" | SLEW = FAST | IOSTANDARD = "LVCMOS33";
NET "host_serial_rxd" LOC = "A16" | IOSTANDARD = "LVCMOS33";
NET "usermem_data<0>" LOC = "V14" | SLEW = FAST | IOSTANDARD = "LVCMOS33";
NET "usermem_data<1>" LOC = "T11" | SLEW = FAST | IOSTANDARD = "LVCMOS33";
NET "usermem_data<2>" LOC = "R11" | SLEW = FAST | IOSTANDARD = "LVCMOS33";

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