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99 lines
3.4 KiB
99 lines
3.4 KiB
// This file is part of the Universal Laboratory (uLab)
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//
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// © 2017 - 2019 Raptor Engineering, LLC
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// All Rights Reserved
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//
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// Licensed under the terms of the AGPL v3
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module control_fpga_top
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(
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// Input clock
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input wire main_12_mhz_clock,
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// Guest FPGA interface
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input wire [3:0] four_bit_output, // Output from the user program to the remote access module
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output wire [3:0] four_bit_input, // Input to the user program from the remote access module
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input wire [7:0] eight_bit_output, // Output from the user program to the remote access module
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output wire [7:0] eight_bit_input, // Input to the user program from the remote access module
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input wire [7:0] led_segment_bus,
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input wire [3:0] led_digit_select,
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// Serial interface
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input wire serial_input,
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output wire serial_output,
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// On-board diagnostic LEDs
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output wire [7:0] led_bank
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);
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parameter RAM_ADDR_BITS = 0;
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// Synthesize 50MHz clock from 12MHz clock
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wire main_50_mhz_clock;
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wire pll_locked;
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SB_PLL40_CORE #(
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.FEEDBACK_PATH("SIMPLE"),
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.DIVR(4'b0000), // DIVR = 0
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.DIVF(7'b1000010), // DIVF = 66
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.DIVQ(3'b100), // DIVQ = 4
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.FILTER_RANGE(3'b001) // FILTER_RANGE = 1
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) system_pll (
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.LOCK(pll_locked),
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.RESETB(1'b1),
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.BYPASS(1'b0),
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.REFERENCECLK(main_12_mhz_clock),
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.PLLOUTCORE(main_50_mhz_clock)
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);
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reg [7:0] diagnostic_led_data = 8'b0;
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wire [15:0] sixteen_bit_output; // Output from the user program to the remote access module
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wire [15:0] sixteen_bit_input; // Input to the user program from the remote access module
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wire [5:0] lcd_data_in_address;
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wire [7:0] lcd_data_in_data;
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wire lcd_data_in_enable;
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assign sixteen_bit_output = 16'b0; // Diable 16 bit input for now
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//assign led_bank = eight_bit_input; // Mirror input to the LEDs
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assign led_bank = diagnostic_led_data; // Show diagnostic data on LEDs
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reg [22:0] slow_clock_divider = 23'b0;
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wire slow_clock;
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reg [1:0] kr_state = 2'b0;
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always @(posedge main_12_mhz_clock) begin
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slow_clock_divider <= slow_clock_divider + 1;
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end
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assign slow_clock = slow_clock_divider[22];
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always @(posedge slow_clock) begin
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kr_state <= kr_state + 1;
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if (pll_locked) begin
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case (kr_state)
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0: diagnostic_led_data <= 8'b00011000;
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1: diagnostic_led_data <= 8'b00100100;
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2: diagnostic_led_data <= 8'b01000010;
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3: diagnostic_led_data <= 8'b10000001;
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endcase
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end else begin
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diagnostic_led_data <= 8'b0;
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end
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end
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assign lcd_data_in_enable = 1'b0; // Disable LCD I/O for now
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assign lcd_data_in_address = 6'b0; // Disable LCD I/O for now
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assign lcd_data_in_data = 8'b0; // Disable LCD I/O for now
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// Instantiate main remote access module
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remote_access #(RAM_ADDR_BITS) remote_access(.main_fifty_clock(main_50_mhz_clock), .remote_access_4_bit_output(four_bit_output),
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.remote_access_4_bit_input(four_bit_input), .remote_access_8_bit_output(eight_bit_output),
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.remote_access_8_bit_input(eight_bit_input), .remote_access_16_bit_output(sixteen_bit_output),
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.remote_access_16_bit_input(sixteen_bit_input),
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.serial_port_receiver(serial_input), .serial_port_transmitter(serial_output), .remote_access_input_enable(1'b0),
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.local_input(8'b0), .seize_serial_tx(1'b0), .serial_tx_data(8'b0), .serial_tx_strobe(1'b0),
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.lcd_data_in_address(lcd_data_in_address), .lcd_data_in_data(lcd_data_in_data), .lcd_data_in_enable(lcd_data_in_enable),
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.led_segment_bus(led_segment_bus), .led_digit_select(led_digit_select));
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endmodule
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