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783 lines
16 KiB
783 lines
16 KiB
/*
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* xsvftool-xpcu - An (X)SVF player for the Xilinx Platform Cable USB
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*
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* Copyright (C) 2011 RIEGL Research ForschungsGmbH
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* Copyright (C) 2011 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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/*
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* Command Reference (EP1)
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* -----------------------
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*
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* Request: T<nn>
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* Response: OK (T<nn>)
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* Configure timing for EP2/JTAG transfers
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*
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* Request: R
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* Response: OK (R)
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* Perform internal and CPLD reset
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*
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* Request: W<n>
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* Response: OK (W<n>)
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* Wait for the CPLD sync signal to become <n>
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*
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* Request: C
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* Response: <nnnnnn> (C)
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* Read out the CPLD verilog checksum
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*
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* Request: B<n>
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* Response: OK (B<n>)
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* Set BUFFER_OE to <n>
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*
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* Request: I<n>
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* Response: OK (I<n>)
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* Set INIT_INT to <n>
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*
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* Request: S
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* Response: <n><m><k><p><x><y><s> (S)
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* Read and reset status bits
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* (<n> = FX2-JTAG-ERR, <m> = CPLD-JTAG-ERR, <k> = INIT_B_INT,
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* <p> = SLOE_INT, <x> = FX2-JTAG-TDO, <y> = CPLD-JTAG-TDO, <s> = SYNC)
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*
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* Request: P
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* Response: <n><m><k><p><x><y><s> (P)
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* Peek status bits without resetting them
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*
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* Request: J<bindata>
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* Response: -- NONE --
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* Execute JTAG transaction (4bit/cycle)
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*
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* Request: X
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* Response: OK (X)
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* Exit. Restore FX2 default settings and enter endless loop
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*
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*
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* Target JTAG Programming (EP2)
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* -----------------------------
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*
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* Raw JTAG transaction codes.
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* (4bit/cycle when T=0, 8bit/cycle otherwise)
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*
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*
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* JTAG Transaction codes
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* ----------------------
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*
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* 0000:
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* NOP
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*
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* 0001 xxxx:
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* Set sync signal to 'xxxx' (engine on CPLD only)
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*
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* 001x:
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* reserved for future use
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*
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* 01xy:
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* JTAG transaction without TDO check. TMS=x, TDI=y
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*
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* 1zxy:
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* JTAG transaction with TDO check. TDO=z, TMS=x, TDI=y
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*
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*
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* FX2 <-> CPLD Interface
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* ----------------------
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*
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* FD[7:0] ---> FD[7:0]
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* CTL0 ---> STROBE_FD (neg)
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* CTL1 ---> STROBE_SHIFT (neg)
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* CTL2 ---> STROBE_PUSH (neg)
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*
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* PC[7:4] <--- SYNC
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* PC3 <--- TDO
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* PC2 <--- CKSUM
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* PC1 <--- INIT_B_INT
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* PC0 <--- ERR
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*
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* PD4 ---> RESET_SYNC
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* PD3 ---> RESET_ERR
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* PD2 ---> INIT_INT
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* PD1 ---> SHIFT_CKSUM
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* PD0 ---> RESET_CKSUM
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*
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*
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* Other FX2 Connections
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* ---------------------
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*
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* PA0 ---> LED_GREEN
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* PA1 ---> LED_RED
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* PA2 <--- SLOE_INT
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* PA3 ---> CPLD_PWR
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* PA5 ---> BUFFER_OE
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*
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* IOE[3] ---> CPLD TCK
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* IOE[4] ---> CPLD TMS
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* IOE[5] <--- CPLD TDO
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* IOE[6] ---> CPLD TDI
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*
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*/
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// #include "fx2.h"
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// #include "fx2regs.h"
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// #include "fx2sdly.h"
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#include "gpifprog_fixed.c"
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// set to '1' on CPLD JTAG error
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BYTE state_err;
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// use quad buffering and larger buffers
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#define ALL_RESOURCES_ON_EP2
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void sleep3us(void)
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{
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SYNCDELAY;
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SYNCDELAY;
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SYNCDELAY;
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SYNCDELAY;
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SYNCDELAY;
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SYNCDELAY;
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SYNCDELAY;
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SYNCDELAY;
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}
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void msleep(WORD ms)
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{
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WORD i;
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while (ms-- > 0) {
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for (i = 0; i < 1000; i += 3)
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sleep3us();
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}
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}
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void setup(void)
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{
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BYTE i;
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/* CPU: 48MHz, don't drive CLKOUT */
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CPUCS = 0x10;
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#ifdef ALL_RESOURCES_ON_EP2
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/* Configure the Endpoints (EP2 => 4x 1kB) */
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EP2CFG = 0xA8; // VALID=1, DIR=0, TYPE=10, SIZE=1, BUF=00
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EP4CFG = 0x00; // VALID=0, DIR=0, TYPE=00, SIZE=0, BUF=00
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EP6CFG = 0x00; // VALID=0, DIR=0, TYPE=00, SIZE=0, BUF=00
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EP8CFG = 0x00; // VALID=0, DIR=0, TYPE=00, SIZE=0, BUF=00
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#else
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/* Configure the Endpoints (default config) */
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EP2CFG = 0xA2; // VALID=1, DIR=0, TYPE=10, SIZE=0, BUF=10
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EP4CFG = 0xA0; // VALID=1, DIR=0, TYPE=10, SIZE=0, BUF=00
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EP6CFG = 0xA2; // VALID=1, DIR=1, TYPE=10, SIZE=0, BUF=10
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EP8CFG = 0xA0; // VALID=1, DIR=1, TYPE=10, SIZE=0, BUF=00
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#endif
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/* USB FIFO */
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FIFORESET = 0x80;
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SYNCDELAY;
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FIFORESET = 2;
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SYNCDELAY;
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FIFORESET = 4;
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SYNCDELAY;
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FIFORESET = 6;
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SYNCDELAY;
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FIFORESET = 8;
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SYNCDELAY;
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FIFORESET = 0;
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SYNCDELAY;
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/* Set WORDWIDE=0 for all FIFOs */
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EP2FIFOCFG &= ~bmWORDWIDE;
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SYNCDELAY;
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EP4FIFOCFG &= ~bmWORDWIDE;
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SYNCDELAY;
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EP6FIFOCFG &= ~bmWORDWIDE;
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SYNCDELAY;
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EP8FIFOCFG &= ~bmWORDWIDE;
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SYNCDELAY;
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/* Initialize GPIF Subsystem */
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GpifInit();
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/* Misc signals on port A */
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PORTACFG = 0;
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OEA = bmBIT0 | bmBIT1 | bmBIT3 | bmBIT5;
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IOA = 0;
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/* FX2 <-> CPLD signals on port C */
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PORTCCFG = 0;
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OEC = 0;
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IOC = 0;
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/* FX2 <-> CPLD signals on port D */
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OED = bmBIT0 | bmBIT1 | bmBIT2 | bmBIT3 | bmBIT4;
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IOD = 0;
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/* TURN ON CPLD VCC */
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PA3 = 1;
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msleep(100);
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/* XC2S256 JTAG on port E */
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OEE = bmBIT3|bmBIT4|bmBIT6;
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IOE = bmBIT3|bmBIT4|bmBIT6;
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/* Set TAP to logic reset state */
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for (i=0; i<16; i++) {
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// TMS is high - just generate a few TCK pulses
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sleep3us();
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IOE &= ~bmBIT3;
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sleep3us();
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IOE |= bmBIT3;
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}
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/* All set up: Let the host find out about the new EP config */
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#if 0
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USBCS |= bmDISCON;
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msleep(10);
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USBCS &= ~bmDISCON;
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#endif
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}
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void unsetup(void)
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{
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WORD i, j;
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/* 1st TURN OFF CPLD VCC */
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PA3 = 0;
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msleep(100);
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/*
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* Restore default configuration as good as possible
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*
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* The idea is that one could load the xilinx firmware without
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* the need to reconnect. Unfortunately it doesn't work. Something
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* important is still different between the FX2 after reset and
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* after running this unsetup() function.
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*/
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GPIFABORT = 0xFF;
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SYNCDELAY;
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CPUCS = 0x02;
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SYNCDELAY;
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IFCONFIG = 0x80;
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SYNCDELAY;
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EP2CFG = 0xA2;
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SYNCDELAY;
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EP4CFG = 0xA0;
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SYNCDELAY;
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EP6CFG = 0xA2;
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SYNCDELAY;
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EP8CFG = 0xA0;
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SYNCDELAY;
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EP2FIFOCFG = 0x05;
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SYNCDELAY;
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EP4FIFOCFG = 0x05;
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SYNCDELAY;
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EP6FIFOCFG = 0x05;
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SYNCDELAY;
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EP8FIFOCFG = 0x05;
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SYNCDELAY;
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FIFORESET = 0x80;
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SYNCDELAY;
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FIFORESET = 2;
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SYNCDELAY;
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FIFORESET = 4;
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SYNCDELAY;
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FIFORESET = 6;
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SYNCDELAY;
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FIFORESET = 8;
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SYNCDELAY;
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FIFORESET = 0;
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SYNCDELAY;
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IOA = 0;
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IOC = 0;
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IOD = 0;
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IOE = 0;
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OEA = 0;
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OEC = 0;
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OED = 0;
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OEE = 0;
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PORTACFG = 0;
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PORTCCFG = 0;
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OEA = 1;
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for (i=0; i<3; i++) {
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PA0 = 1;
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for (j=0; j<3000; j++) sleep3us();
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PA1 = 0;
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for (j=0; j<3000; j++) sleep3us();
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}
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OEA = 0;
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// just ack everything and wait
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while (1) {
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if((EP1OUTCS & bmBIT1) == 0) {
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EP1OUTBC = 0xff; SYNCDELAY;
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}
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if((EP2CS & bmBIT2) == 0) {
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EP2BCL = 0xff; SYNCDELAY;
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}
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}
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}
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BYTE nibble2hex(BYTE v)
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{
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return "0123456789ABCDEF"[v&0x0f];
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}
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BYTE hex2nibble(BYTE v)
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{
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if (v >= '0' && v <= '9')
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return v - '0';
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if (v >= 'a' && v <= 'f')
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return 0x0A + v - 'a';
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if (v >= 'A' && v <= 'F')
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return 0x0A + v - 'A';
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return 0;
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}
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xdata at (0xE400 + 64) volatile BYTE GPIF_WAVE2_LEN0;
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xdata at (0xE400 + 66) volatile BYTE GPIF_WAVE2_LEN2;
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void proc_command_t(BYTE t)
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{
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if (t == 0) {
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GPIFWFSELECT = 0x4E; SYNCDELAY;
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} else {
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GPIFWFSELECT = 0x4A; SYNCDELAY;
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GPIF_WAVE2_LEN0 = t; SYNCDELAY;
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GPIF_WAVE2_LEN2 = t; SYNCDELAY;
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}
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EP1INBUF[0] = 'O'; SYNCDELAY;
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EP1INBUF[1] = 'K'; SYNCDELAY;
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EP1INBUF[2] = ' '; SYNCDELAY;
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EP1INBUF[3] = '('; SYNCDELAY;
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EP1INBUF[4] = 'T'; SYNCDELAY;
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EP1INBUF[5] = nibble2hex((t >> 4) & 0x0f); SYNCDELAY;
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EP1INBUF[6] = nibble2hex((t >> 0) & 0x0f); SYNCDELAY;
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EP1INBUF[7] = ')'; SYNCDELAY;
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EP1INBC = 8; SYNCDELAY;
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}
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void proc_command_r(void)
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{
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BYTE i, *p = "OK (R)";
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/* Reset TAP to logic reset state */
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IOE = bmBIT3|bmBIT4|bmBIT6;
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for (i=0; i<16; i++) {
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// TMS is high - just generate a few TCK pulses
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sleep3us();
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IOE &= ~bmBIT3;
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sleep3us();
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IOE |= bmBIT3;
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}
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/* Reset speed to max. */
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GPIFWFSELECT = 0x4E; SYNCDELAY;
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/* Reset JTAG error state */
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state_err = 0;
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/* Reset LEDs and BUFFER_OE */
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PA0 = PA1 = PA5 = 0;
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/* Assert CPLD reset pins */
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IOD = bmBIT0 | bmBIT3 | bmBIT4;
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SYNCDELAY;
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IOD |= bmBIT1;
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SYNCDELAY;
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IOD = 0;
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/* Send response */
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for (i = 0; p[i]; i++) {
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EP1INBUF[i] = p[i]; SYNCDELAY;
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}
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EP1INBC = i; SYNCDELAY;
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}
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void proc_bulkdata(void);
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void proc_command_w_ok(BYTE v)
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{
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EP1INBUF[0] = 'O'; SYNCDELAY;
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EP1INBUF[1] = 'K'; SYNCDELAY;
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EP1INBUF[2] = ' '; SYNCDELAY;
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EP1INBUF[3] = '('; SYNCDELAY;
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EP1INBUF[4] = 'W'; SYNCDELAY;
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EP1INBUF[5] = nibble2hex(v); SYNCDELAY;
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EP1INBUF[6] = ')'; SYNCDELAY;
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EP1INBC = 7; SYNCDELAY;
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}
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void proc_command_w_timeout(BYTE v)
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{
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EP1INBUF[0] = 'T'; SYNCDELAY;
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EP1INBUF[1] = 'I'; SYNCDELAY;
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EP1INBUF[2] = 'M'; SYNCDELAY;
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EP1INBUF[3] = 'E'; SYNCDELAY;
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EP1INBUF[4] = 'O'; SYNCDELAY;
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EP1INBUF[5] = 'U'; SYNCDELAY;
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EP1INBUF[6] = 'T'; SYNCDELAY;
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EP1INBUF[7] = '!'; SYNCDELAY;
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EP1INBUF[8] = ' '; SYNCDELAY;
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EP1INBUF[9] = 'S'; SYNCDELAY;
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EP1INBUF[10] = '='; SYNCDELAY;
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EP1INBUF[11] = nibble2hex(IOC >> 4); SYNCDELAY;
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EP1INBUF[12] = ' '; SYNCDELAY;
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EP1INBUF[13] = '('; SYNCDELAY;
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EP1INBUF[14] = 'W'; SYNCDELAY;
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EP1INBUF[15] = nibble2hex(v); SYNCDELAY;
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EP1INBUF[16] = ')'; SYNCDELAY;
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EP1INBC = 17; SYNCDELAY;
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}
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void proc_command_w(BYTE v)
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{
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WORD i, j;
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for (i = 0; i < 1000; i++)
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for (j = 0; j < 1000; j++)
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{
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/* check for wait condition */
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if ((IOC >> 4) == v) {
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proc_command_w_ok(v);
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return;
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}
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/* check for data on EP2 */
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if((EP2CS & bmBIT2) == 0) {
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PA0 = 1;
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proc_bulkdata();
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PA0 = 0;
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}
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}
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proc_command_w_timeout(v);
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}
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void proc_command_c(void)
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{
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BYTE i, j, buf;
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/* Reset chksum register */
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PD0 = 1;
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PD1 = 0;
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SYNCDELAY;
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PD1 = 1;
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SYNCDELAY;
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PD0 = 0;
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PD1 = 0;
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for (i = 0; i < 6; i++) {
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buf = 0;
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for (j = 0; j < 4; j++) {
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buf = buf << 1 | PC2;
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SYNCDELAY;
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PD1 = 1;
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SYNCDELAY;
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PD1 = 0;
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}
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EP1INBUF[i] = nibble2hex(buf); SYNCDELAY;
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}
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EP1INBUF[6] = ' '; SYNCDELAY;
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EP1INBUF[7] = '('; SYNCDELAY;
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EP1INBUF[8] = 'C'; SYNCDELAY;
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EP1INBUF[9] = ')'; SYNCDELAY;
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EP1INBC = 10; SYNCDELAY;
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}
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void proc_command_b(BYTE v)
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{
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PA5 = v;
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EP1INBUF[0] = 'O'; SYNCDELAY;
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EP1INBUF[1] = 'K'; SYNCDELAY;
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EP1INBUF[2] = ' '; SYNCDELAY;
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EP1INBUF[3] = '('; SYNCDELAY;
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EP1INBUF[4] = 'B'; SYNCDELAY;
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EP1INBUF[5] = v ? '1' : '0'; SYNCDELAY;
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EP1INBUF[6] = ')'; SYNCDELAY;
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EP1INBC = 7; SYNCDELAY;
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}
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void proc_command_i(BYTE v)
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{
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PD2 = v;
|
|
|
|
EP1INBUF[0] = 'O'; SYNCDELAY;
|
|
EP1INBUF[1] = 'K'; SYNCDELAY;
|
|
EP1INBUF[2] = ' '; SYNCDELAY;
|
|
EP1INBUF[3] = '('; SYNCDELAY;
|
|
EP1INBUF[4] = 'I'; SYNCDELAY;
|
|
EP1INBUF[5] = v ? '1' : '0'; SYNCDELAY;
|
|
EP1INBUF[6] = ')'; SYNCDELAY;
|
|
EP1INBC = 7; SYNCDELAY;
|
|
}
|
|
|
|
void proc_command_s(void)
|
|
{
|
|
EP1INBUF[0] = PC0 ? '1' : '0'; SYNCDELAY;
|
|
EP1INBUF[1] = state_err ? '1' : '0'; SYNCDELAY;
|
|
EP1INBUF[2] = PC1 ? '1' : '0'; SYNCDELAY;
|
|
EP1INBUF[3] = PA2 ? '1' : '0'; SYNCDELAY;
|
|
EP1INBUF[4] = PC3 ? '1' : '0'; SYNCDELAY;
|
|
EP1INBUF[5] = (IOE & bmBIT5) ? '1' : '0'; SYNCDELAY;
|
|
EP1INBUF[6] = nibble2hex(IOC >> 4); SYNCDELAY;
|
|
EP1INBUF[7] = ' '; SYNCDELAY;
|
|
EP1INBUF[8] = '('; SYNCDELAY;
|
|
EP1INBUF[9] = 'S'; SYNCDELAY;
|
|
EP1INBUF[10] = ')'; SYNCDELAY;
|
|
EP1INBC = 11; SYNCDELAY;
|
|
|
|
// reset error state
|
|
state_err = 0;
|
|
IOD = bmBIT3;
|
|
SYNCDELAY;
|
|
SYNCDELAY;
|
|
IOD &= ~bmBIT3;
|
|
}
|
|
|
|
void proc_command_p(void)
|
|
{
|
|
EP1INBUF[0] = PC0 ? '1' : '0'; SYNCDELAY;
|
|
EP1INBUF[1] = state_err ? '1' : '0'; SYNCDELAY;
|
|
EP1INBUF[2] = PC1 ? '1' : '0'; SYNCDELAY;
|
|
EP1INBUF[3] = PA2 ? '1' : '0'; SYNCDELAY;
|
|
EP1INBUF[4] = PC3 ? '1' : '0'; SYNCDELAY;
|
|
EP1INBUF[5] = (IOE & bmBIT5) ? '1' : '0'; SYNCDELAY;
|
|
EP1INBUF[6] = nibble2hex(IOC >> 4); SYNCDELAY;
|
|
EP1INBUF[7] = ' '; SYNCDELAY;
|
|
EP1INBUF[8] = '('; SYNCDELAY;
|
|
EP1INBUF[9] = 'P'; SYNCDELAY;
|
|
EP1INBUF[10] = ')'; SYNCDELAY;
|
|
EP1INBC = 11; SYNCDELAY;
|
|
}
|
|
|
|
BYTE proc_command_j_exec_skip_next;
|
|
void proc_command_j_exec(BYTE cmd)
|
|
{
|
|
if (proc_command_j_exec_skip_next) {
|
|
proc_command_j_exec_skip_next = 0;
|
|
return;
|
|
}
|
|
if (cmd == 0x00)
|
|
return;
|
|
if (cmd == 0x01) {
|
|
// 0001 xxxx: Set sync signal to 'xxxx' (engine on CPLD only)
|
|
proc_command_j_exec_skip_next = 1;
|
|
return;
|
|
}
|
|
if ((cmd & 0x0c) == 0x04)
|
|
{
|
|
// 01xy: JTAG transaction without TDO check. TMS=x, TDI=y
|
|
|
|
/* set tms line */
|
|
if (cmd & 0x02)
|
|
IOE |= bmBIT4;
|
|
else
|
|
IOE &= ~bmBIT4;
|
|
|
|
/* set tdi line */
|
|
if (cmd & 0x01)
|
|
IOE |= bmBIT6;
|
|
else
|
|
IOE &= ~bmBIT6;
|
|
|
|
/* generate tck pulse */
|
|
SYNCDELAY;
|
|
IOE &= ~bmBIT3;
|
|
sleep3us();
|
|
IOE |= bmBIT3;
|
|
SYNCDELAY;
|
|
|
|
return;
|
|
}
|
|
if ((cmd & 0x08) == 0x08)
|
|
{
|
|
// 1zxy: JTAG transaction with TDO check. TDO=z, TMS=x, TDI=y
|
|
|
|
/* set tms line */
|
|
if (cmd & 0x02)
|
|
IOE |= bmBIT4;
|
|
else
|
|
IOE &= ~bmBIT4;
|
|
|
|
/* set tdi line */
|
|
if (cmd & 0x01)
|
|
IOE |= bmBIT6;
|
|
else
|
|
IOE &= ~bmBIT6;
|
|
|
|
/* generate tck pulse */
|
|
SYNCDELAY;
|
|
IOE &= ~bmBIT3;
|
|
sleep3us();
|
|
IOE |= bmBIT3;
|
|
SYNCDELAY;
|
|
|
|
/* perform tdo check */
|
|
if (((cmd & 0x04) == 0) != ((IOE & bmBIT5) == 0))
|
|
state_err = 1;
|
|
|
|
return;
|
|
}
|
|
}
|
|
|
|
void proc_command_j(BYTE len)
|
|
{
|
|
BYTE i;
|
|
proc_command_j_exec_skip_next = 0;
|
|
for (i = 1; i < len; i++) {
|
|
BYTE cmd = EP1OUTBUF[i];
|
|
proc_command_j_exec(cmd & 0x0f);
|
|
proc_command_j_exec(cmd >> 4);
|
|
}
|
|
}
|
|
|
|
void proc_command_x(void)
|
|
{
|
|
EP1INBUF[0] = 'O'; SYNCDELAY;
|
|
EP1INBUF[1] = 'K'; SYNCDELAY;
|
|
EP1INBUF[2] = ' '; SYNCDELAY;
|
|
EP1INBUF[3] = '('; SYNCDELAY;
|
|
EP1INBUF[4] = 'X'; SYNCDELAY;
|
|
EP1INBUF[5] = ')'; SYNCDELAY;
|
|
EP1INBC = 6; SYNCDELAY;
|
|
|
|
/* accept new data on EP1OUT */
|
|
EP1OUTBC = 0xff; SYNCDELAY;
|
|
|
|
unsetup();
|
|
}
|
|
|
|
void proc_command(void)
|
|
{
|
|
BYTE len, cmd;
|
|
|
|
/* process command(s) */
|
|
len = EP1OUTBC;
|
|
cmd = EP1OUTBUF[0];
|
|
|
|
if (cmd == 'T' && len == 3)
|
|
proc_command_t((hex2nibble(EP1OUTBUF[1]) << 4) | hex2nibble(EP1OUTBUF[2]));
|
|
else if (cmd == 'R' && len == 1)
|
|
proc_command_r();
|
|
else if (cmd == 'W' && len == 2)
|
|
proc_command_w(hex2nibble(EP1OUTBUF[1]));
|
|
else if (cmd == 'C' && len == 1)
|
|
proc_command_c();
|
|
else if (cmd == 'B' && len == 2)
|
|
proc_command_b(EP1OUTBUF[1] == '1');
|
|
else if (cmd == 'I' && len == 2)
|
|
proc_command_i(EP1OUTBUF[1] == '1');
|
|
else if (cmd == 'S' && len == 1)
|
|
proc_command_s();
|
|
else if (cmd == 'P' && len == 1)
|
|
proc_command_p();
|
|
else if (cmd == 'J')
|
|
proc_command_j(len);
|
|
else if (cmd == 'X')
|
|
proc_command_x();
|
|
else
|
|
{
|
|
/* send error response */
|
|
EP1INBUF[0] = 'E'; SYNCDELAY;
|
|
EP1INBUF[1] = 'R'; SYNCDELAY;
|
|
EP1INBUF[2] = 'R'; SYNCDELAY;
|
|
EP1INBUF[3] = 'O'; SYNCDELAY;
|
|
EP1INBUF[4] = 'R'; SYNCDELAY;
|
|
EP1INBUF[5] = '!'; SYNCDELAY;
|
|
EP1INBC = 6; SYNCDELAY;
|
|
}
|
|
|
|
/* accept new data on EP1OUT */
|
|
EP1OUTBC = 0xff; SYNCDELAY;
|
|
}
|
|
|
|
void proc_bulkdata(void)
|
|
{
|
|
WORD len;
|
|
|
|
len = (EP2BCH << 8) | EP2BCL;
|
|
if (len == 0)
|
|
{
|
|
/* ignore this and accept data on EP2 */
|
|
EP2BCL = 0xff; SYNCDELAY;
|
|
}
|
|
#if 0
|
|
else if (len == 1)
|
|
{
|
|
while ((GPIFTRIG & 0x80) == 0) { /* GPIF is busy */ }
|
|
|
|
/* transfer single byte */
|
|
XGPIFSGLDATH = 0; SYNCDELAY;
|
|
XGPIFSGLDATLX = EP2FIFOBUF[0]; SYNCDELAY;
|
|
|
|
/* accept new data on EP2 */
|
|
EP2BCL = 0xff; SYNCDELAY;
|
|
}
|
|
#endif
|
|
else
|
|
{
|
|
while ((GPIFTRIG & 0x80) == 0) { /* GPIF is busy */ }
|
|
|
|
/* pass pkt to GPIF master */
|
|
EP2GPIFTCH = EP2BCH;
|
|
EP2GPIFTCL = EP2BCL;
|
|
EP2BCL = 0x00;
|
|
EP2GPIFTRIG = 0xff;
|
|
}
|
|
}
|
|
|
|
void main(void)
|
|
{
|
|
state_err = 0;
|
|
|
|
setup();
|
|
|
|
/* accept data on EP2 */
|
|
EP2BCL = 0xff; SYNCDELAY; // 1st buffer
|
|
EP2BCL = 0xff; SYNCDELAY; // 2nd buffer
|
|
#ifdef ALL_RESOURCES_ON_EP2
|
|
EP2BCL = 0xff; SYNCDELAY; // 3rd buffer
|
|
EP2BCL = 0xff; SYNCDELAY; // 4th buffer
|
|
#endif
|
|
|
|
while (1)
|
|
{
|
|
/* check for data on EP1 */
|
|
if((EP1OUTCS & bmBIT1) == 0) {
|
|
PA1 = 1;
|
|
proc_command();
|
|
PA1 = 0;
|
|
}
|
|
|
|
/* check for data on EP2 */
|
|
if((EP2CS & bmBIT2) == 0) {
|
|
PA0 = 1;
|
|
proc_bulkdata();
|
|
PA0 = 0;
|
|
}
|
|
}
|
|
}
|
|
|