`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
// (c) 2014 Timothy Pearson, Raptor Engineering
// Released into the Public Domain
//
//////////////////////////////////////////////////////////////////////////////////

module logic_analyzer_data_storage(
	input clk,
	input [(RAM_WIDTH-1):0] dina,
	input [(RAM_WIDTH-1):0] dinb,
	input [(RAM_ADDR_BITS-1):0] addra,
	input [(RAM_ADDR_BITS-1):0] addrb,
	input wea,
	input web,
	output reg [(RAM_WIDTH-1):0] douta,
	output reg [(RAM_WIDTH-1):0] doutb);

	parameter RAM_ADDR_BITS = 11;
	parameter RAM_WIDTH = 64;
	
	// Xilinx specific directive
	(* RAM_STYLE="BLOCK" *)
	
	reg [RAM_WIDTH-1:0] logic_analyzer_data_storage_ram [(2**RAM_ADDR_BITS)-1:0];

	// Initial RAM values for debugging
	integer index;
	initial begin
		for (index = 0; index < ((2**RAM_ADDR_BITS)-1); index = index + 2) begin
			logic_analyzer_data_storage_ram[index+0] = {(RAM_WIDTH/4){4'ha}};
			logic_analyzer_data_storage_ram[index+1] = {(RAM_WIDTH/4){4'h5}};
		end
	end

	// Registered
	always @(posedge clka) begin
		douta <= logic_analyzer_data_storage_ram[addra];
		if (wea) begin
			logic_analyzer_data_storage_ram[addra] <= dina;
			douta <= dina;
		end
	end

	always @(posedge clkb) begin
		doutb <= logic_analyzer_data_storage_ram[addrb];
		if (web) begin
			logic_analyzer_data_storage_ram[addrb] <= dinb;
			doutb <= dinb;
		end
	end

// 	// Unregistered
// 	always @(posedge clka) begin
// 		if (wea) begin
// 			logic_analyzer_data_storage_ram[addra] <= dina;
// 		end
// 	end
// 	assign douta = logic_analyzer_data_storage_ram[addra];
// 
// 	always @(posedge clkb) begin
// 		if (web) begin
// 			logic_analyzer_data_storage_ram[addrb] <= dinb;
// 		end
// 	end
// 	assign doutb = logic_analyzer_data_storage_ram[addrb];

endmodule