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321 lines
10 KiB
321 lines
10 KiB
4 years ago
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/*
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* accore.c -- core aclib functions
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* Written by Andrew Church <achurch@achurch.org>
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*
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* This file is part of transcode, a video stream processing tool.
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* transcode is free software, distributable under the terms of the GNU
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* General Public License (version 2 or later). See the file COPYING
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* for details.
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*/
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#include "ac.h"
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#include "ac_internal.h"
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#include "imgconvert.h"
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#include <stdio.h>
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#include <string.h>
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#if defined(ARCH_X86) || defined(ARCH_X86_64)
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static int cpuinfo_x86(void);
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#endif
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/*************************************************************************/
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/* Library initialization function. Determines CPU features, then calls
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* all initialization subfunctions with appropriate flags. Returns 1 on
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* success, 0 on failure. This function can be called multiple times to
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* change the set of acceleration features to be used. */
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int ac_init(int accel)
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{
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accel &= ac_cpuinfo();
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if (!ac_average_init(accel)
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|| !ac_imgconvert_init(accel)
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|| !ac_memcpy_init(accel)
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|| !ac_rescale_init(accel)
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) {
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return 0;
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}
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return 1;
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}
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/*************************************************************************/
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/* Returns the set of acceleration features supported by this CPU. */
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int ac_cpuinfo(void)
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{
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#if defined(ARCH_X86) || defined(ARCH_X86_64)
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return cpuinfo_x86();
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#else
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return 0;
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#endif
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}
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/*************************************************************************/
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/* Returns the endianness of this CPU (AC_BIG_ENDIAN or AC_LITTLE_ENDIAN). */
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int ac_endian(void)
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{
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volatile int test;
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test = 1;
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if (*((uint8_t *)&test))
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return AC_LITTLE_ENDIAN;
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else
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return AC_BIG_ENDIAN;
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}
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/*************************************************************************/
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/* Utility routine to convert a set of flags to a descriptive string. The
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* string is stored in a static buffer overwritten each call. `filter'
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* selects whether to filter out flags not supported by the CPU. */
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const char *ac_flagstotext(int accel)
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{
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static char retbuf[1000];
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if (!accel)
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return "none";
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snprintf(retbuf, sizeof(retbuf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
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accel & AC_SSE5 ? " sse5" : "",
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accel & AC_SSE4A ? " sse4a" : "",
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accel & AC_SSE42 ? " sse42" : "",
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accel & AC_SSE41 ? " sse41" : "",
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accel & AC_SSSE3 ? " ssse3" : "",
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accel & AC_SSE3 ? " sse3" : "",
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accel & AC_SSE2 ? " sse2" : "",
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accel & AC_SSE ? " sse" : "",
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accel & AC_3DNOWEXT ? " 3dnowext" : "",
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accel & AC_3DNOW ? " 3dnow" : "",
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accel & AC_MMXEXT ? " mmxext" : "",
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accel & AC_MMX ? " mmx" : "",
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accel & AC_CMOVE ? " cmove" : "",
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accel & (AC_IA32ASM|AC_AMD64ASM) ? " asm" : "");
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return *retbuf ? retbuf+1 : retbuf; /* skip initial space */
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}
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/* Utility routine to parse a comma-separate descriptive string to the
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corrisponding flag. The reverse of ac_flagstotext.
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Returns 1 on success, 0 on failure */
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#define AC_FLAG_LEN 16
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int ac_parseflags(const char *text, int *accel)
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{
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int parsed = 1, done = 0;
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if (!text || !accel)
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return 0;
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#if defined(ARCH_X86) || defined(ARCH_X86_64)
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*accel = 0;
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while (parsed && !done) {
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char buf[AC_FLAG_LEN + 1] = { '\0' };
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const char *comma = strchr(text, ',');
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if (!comma) {
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strncpy(buf, text, AC_FLAG_LEN);
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done = 1;
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} else {
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/* parse the remaining and exit*/
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size_t len = (comma - text);
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if (len > AC_FLAG_LEN)
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len = AC_FLAG_LEN;
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strncpy(buf, text, len);
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}
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//fprintf(stderr, "(%s) buf=[%s]\n", __func__, buf);
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if (strcasecmp(buf, "C") == 0) // dummy for "no accel"
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*accel |= 0;
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#ifdef ARCH_X86
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else if (strcasecmp(buf, "asm" ) == 0)
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*accel |= AC_IA32ASM;
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#endif
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#ifdef ARCH_X86_64
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else if (strcasecmp(buf, "asm" ) == 0)
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*accel |= AC_AMD64ASM;
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#endif
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else if (strcasecmp(buf, "mmx" ) == 0)
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*accel |= AC_MMX;
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else if (strcasecmp(buf, "mmxext" ) == 0)
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*accel |= AC_MMXEXT;
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else if (strcasecmp(buf, "3dnow" ) == 0)
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*accel |= AC_3DNOW;
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else if (strcasecmp(buf, "3dnowext") == 0)
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*accel |= AC_3DNOWEXT;
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else if (strcasecmp(buf, "sse" ) == 0)
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*accel |= AC_SSE;
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else if (strcasecmp(buf, "sse2" ) == 0)
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*accel |= AC_SSE2;
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else if (strcasecmp(buf, "sse3" ) == 0)
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*accel |= AC_SSE3;
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else if (strcasecmp(buf, "ssse3" ) == 0)
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*accel |= AC_SSSE3;
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else if (strcasecmp(buf, "sse41" ) == 0)
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*accel |= AC_SSE41;
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else if (strcasecmp(buf, "sse42" ) == 0)
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*accel |= AC_SSE42;
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else if (strcasecmp(buf, "sse4a" ) == 0)
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*accel |= AC_SSE4A;
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else if (strcasecmp(buf, "sse5" ) == 0)
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*accel |= AC_SSE5;
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else
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parsed = 0;
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text = comma + 1;
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}
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#endif
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return parsed;
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}
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#undef AC_FLAG_LEN
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/*************************************************************************/
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/*************************************************************************/
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/* Private functions to return acceleration flags corresponding to available
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* CPU features for various CPUs. Currently only x86 is supported. */
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/*************************************************************************/
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#if defined(ARCH_X86) || defined(ARCH_X86_64)
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#ifdef ARCH_X86_64
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# define EAX "%%rax"
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# define EBX "%%rbx"
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# define ESI "%%rsi"
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# define PUSHF "pushfq"
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# define POPF "popfq"
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#else
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# define EAX "%%eax"
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# define EBX "%%ebx"
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# define ESI "%%esi"
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# define PUSHF "pushfl"
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# define POPF "popfl"
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#endif
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/* Macro to execute the CPUID instruction with EAX = func. Results are
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* placed in ret_a (EAX), ret_b (EBX), ret_c (ECX), and ret_d (EDX), which
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* must be lvalues. Note that we save and restore EBX (RBX on x86-64)
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* because it is the PIC register. */
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#define CPUID(func,ret_a,ret_b,ret_c,ret_d) \
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asm("mov "EBX", "ESI"; cpuid; xchg "EBX", "ESI \
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: "=a" (ret_a), "=S" (ret_b), "=c" (ret_c), "=d" (ret_d) \
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: "a" (func))
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/* Various CPUID flags. The second word of the macro name indicates the
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* function (1: function 1, X1: function 0x80000001) and register (D: EDX)
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* to which the value belongs. */
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#define CPUID_1D_CMOVE (1UL<<15)
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#define CPUID_1D_MMX (1UL<<23)
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#define CPUID_1D_SSE (1UL<<25)
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#define CPUID_1D_SSE2 (1UL<<26)
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#define CPUID_1C_SSE3 (1UL<< 0)
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#define CPUID_1C_SSSE3 (1UL<< 9)
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#define CPUID_1C_SSE41 (1UL<<19)
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#define CPUID_1C_SSE42 (1UL<<20)
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#define CPUID_X1D_AMD_MMXEXT (1UL<<22) /* AMD only */
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#define CPUID_X1D_AMD_3DNOW (1UL<<31) /* AMD only */
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#define CPUID_X1D_AMD_3DNOWEXT (1UL<<30) /* AMD only */
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#define CPUID_X1D_CYRIX_MMXEXT (1UL<<24) /* Cyrix only */
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#define CPUID_X1C_AMD_SSE4A (1UL<< 6) /* AMD only */
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#define CPUID_X1C_AMD_SSE5 (1UL<<11) /* AMD only */
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static int cpuinfo_x86(void)
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{
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uint32_t eax, ebx, ecx, edx;
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uint32_t cpuid_max, cpuid_ext_max; /* Maximum CPUID function numbers */
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union {
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char string[13];
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struct { uint32_t ebx, edx, ecx; } regs;
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} cpu_vendor; /* 12-byte CPU vendor string + trailing null */
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uint32_t cpuid_1D, cpuid_1C, cpuid_X1C, cpuid_X1D;
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int accel;
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/* First see if the CPUID instruction is even available. We try to
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* toggle bit 21 (ID) of the flags register; if the bit changes, then
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* CPUID is available. */
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asm(PUSHF" \n\
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pop "EAX" \n\
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mov %%eax, %%edx \n\
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xor $0x200000, %%eax \n\
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push "EAX" \n\
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"POPF" \n\
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"PUSHF" \n\
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pop "EAX" \n\
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xor %%edx, %%eax"
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: "=a" (eax) : : "edx");
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if (!eax)
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return 0;
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/* Determine the maximum function number available, and save the vendor
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* string */
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CPUID(0, cpuid_max, ebx, ecx, edx);
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cpu_vendor.regs.ebx = ebx;
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cpu_vendor.regs.ecx = ecx;
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cpu_vendor.regs.edx = edx;
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cpu_vendor.string[12] = 0;
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cpuid_ext_max = 0; /* FIXME: how do early CPUs respond to 0x80000000? */
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CPUID(0x80000000, cpuid_ext_max, ebx, ecx, edx);
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/* Read available features */
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cpuid_1D = cpuid_1C = cpuid_X1C = cpuid_X1D = 0;
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if (cpuid_max >= 1)
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CPUID(1, eax, ebx, cpuid_1C, cpuid_1D);
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if (cpuid_ext_max >= 0x80000001)
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CPUID(0x80000001, eax, ebx, cpuid_X1C, cpuid_X1D);
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/* Convert to acceleration flags */
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#ifdef ARCH_X86_64
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accel = AC_AMD64ASM; /* but not IA32! (register size issues) */
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#else
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accel = AC_IA32ASM;
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#endif
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if (cpuid_1D & CPUID_1D_CMOVE)
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accel |= AC_CMOVE;
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if (cpuid_1D & CPUID_1D_MMX)
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accel |= AC_MMX;
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if (cpuid_1D & CPUID_1D_SSE)
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accel |= AC_SSE;
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if (cpuid_1D & CPUID_1D_SSE2)
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accel |= AC_SSE2;
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if (cpuid_1C & CPUID_1C_SSE3)
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accel |= AC_SSE3;
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if (cpuid_1C & CPUID_1C_SSSE3)
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accel |= AC_SSSE3;
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if (cpuid_1C & CPUID_1C_SSE41)
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accel |= AC_SSE41;
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if (cpuid_1C & CPUID_1C_SSE42)
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accel |= AC_SSE42;
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if (strcmp(cpu_vendor.string, "AuthenticAMD") == 0) {
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if (cpuid_X1D & CPUID_X1D_AMD_MMXEXT)
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accel |= AC_MMXEXT;
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if (cpuid_X1D & CPUID_X1D_AMD_3DNOW)
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accel |= AC_3DNOW;
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if (cpuid_X1D & CPUID_X1D_AMD_3DNOWEXT)
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accel |= AC_3DNOWEXT;
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if (cpuid_X1C & CPUID_X1C_AMD_SSE4A)
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accel |= AC_SSE4A;
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if (cpuid_X1C & CPUID_X1C_AMD_SSE5)
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accel |= AC_SSE5;
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} else if (strcmp(cpu_vendor.string, "CyrixInstead") == 0) {
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if (cpuid_X1D & CPUID_X1D_CYRIX_MMXEXT)
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accel |= AC_MMXEXT;
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}
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/* And return */
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return accel;
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}
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#endif /* ARCH_X86 || ARCH_X86_64 */
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/*************************************************************************/
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/*
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* Local variables:
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* c-file-style: "stroustrup"
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* c-file-offsets: ((case-label . *) (statement-case-intro . *))
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* indent-tabs-mode: nil
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* End:
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*
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* vim: expandtab shiftwidth=4:
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*/
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